Multi-gate transistor

• US 10,121,791 B2
• Filed: 11/21/2017
• Issued: 11/06/2018
• Est. Priority Date: 01/24/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., Samsung Electronics Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yu, Hyun Kwan, Kim, Hyo Jin, Shin, Dong Suk, Yi, Ji Hye, Ha, Ryong
• Primary Examiner(s): Malek, Maliheh
• Application Number:
  US15/819,309
• Publication Number:
  US 20180211959A1
• Time in Patent Office: 350 Days
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A semiconductor device includes a substrate, first through fourth gate electrodes, and first through fifth fin active pattern. A first recess which is formed in the substrate between the first and second gate electrodes intersecting the second fin active pattern, is filled with a first source/drain region, and has a first depth in a third direction perpendicular to the first and second directions. A second recess which is formed in the substrate between the third and fourth gate electrodes intersecting the second fin active pattern, is filled with a second source/drain region, and has a second depth in the third direction. A third recess which is formed in the substrate between the second and third gate electrodes intersecting the second fin active pattern, is filled with a third source/drain region, and has a third depth in the third direction. The third depth is greater than the first and second depths.

Claims

1. A semiconductor device comprising:

a substrate;

first through fourth gate electrodes extending in a first direction on the substrate and being sequentially separated from each other in a second direction perpendicular to the first direction;

a first fin active pattern extending in the second direction and intersecting the second and third gate electrodes;

a second fin active pattern extending in the second direction, being separated from the first fin active pattern in the first direction, and intersecting the first through fourth gate electrodes;

a third fin active pattern extending in the second direction, being separated from the second fin active pattern in the first direction, and intersecting the first and second gate electrodes;

a fourth fin active pattern extending in the second direction, being separated from the third fin active pattern in the second direction, and intersecting the third and fourth gate electrodes;

a fifth fin active pattern extending in the second direction, being separated from the third and fourth fin active patterns in the first direction, and intersecting the first through fourth gate electrodes;

a first recess in the substrate between the first and second gate electrodes intersecting the second fin active pattern, the first recess being filled with a first source/drain region, and having a first depth in a third direction perpendicular to the first and second directions;

a second recess in the substrate between the third and fourth gate electrodes intersecting the second fin active pattern, the second recess being filled with a second source/drain region, and having a second depth in the third direction; and

a third recess which in the substrate between the second and third gate electrodes intersecting the second fin active pattern, is the third recess being filled with a third source/drain region, and having a third depth in the third direction,

wherein the third depth is greater than the first depth and the second depth.

2. The semiconductor device of claim 1, wherein a third width in the second direction of the third recess is greater than a first width in the second direction of the first recess and a second width in the second direction of the second recess.

3. The semiconductor device of claim 2, wherein the first width in the second direction of the first recess is different from the second width in the second direction of the second recess.

4. The semiconductor device of claim 1, wherein the first depth in the third direction of the first recess is different from the second depth in the third direction of the second recess.

5. The semiconductor device of claim 1, wherein a first distance between a second portion of the second gate electrode intersecting the first fin active pattern and a second portion of the third gate electrode intersecting the first fin active pattern is smaller than a second distance between a first portion of the second gate electrode intersecting the second fin active pattern and a first portion of the third gate electrode intersecting the second fin active pattern.

6. The semiconductor device of claim 5, wherein a third distance between a third portion of the second gate electrode intersecting the third fin active pattern and a third portion of the third gate electrode intersecting the fourth fin active pattern is smaller than the second distance.

7. The semiconductor device of claim 1, wherein the third recess has a slope profile in which the third recess becomes narrower in the second direction as a distance from a top of the third recess to the substrate is reduced.

8. The semiconductor device of claim 1, wherein a lower portion of the third recess is U-shaped.

9. A semiconductor device comprising:

a substrate comprising a first region and a second region;

a first gate electrode extending in a first direction on the first region;

a second gate electrode extending in the first direction on the first region and being separated from the first gate electrode in a second direction perpendicular to the first direction;

a third gate electrode extending in the first direction on the second region and being separated from the second gate electrode in the second direction;

a fourth gate electrode extending in the first direction on the second region and being separated from the third gate electrode in the second direction;

a first fin active pattern extending in the second direction on the first and second regions and intersecting the first through fourth gate electrodes;

a second fin active pattern extending in the second direction on the first region, being separated from the first fin active pattern in the first direction, and intersecting the first and second gate electrodes;

a third fin active pattern extending in the second direction on the second region, being separated from the second fin active pattern in the second direction, and intersecting the third and fourth gate electrodes;

a first source/drain region in the first region between the first and second gate electrodes intersecting the first fin active pattern and having a first depth in a third direction perpendicular to the first and second directions;

a second source/drain region in the second region between the third and fourth gate electrodes intersecting the first fin active pattern and having a second depth in the third direction; and

a third source/drain region in the first and second regions between the second and third gate electrodes intersecting the first fin active pattern and having a third depth in the third direction,

wherein the third depth is greater than the first depth and the second depth.

10. The semiconductor device of claim 9, wherein a third width in the second direction of the third source/drain region is greater than a first width in the second direction of the first source/drain region and a second width in the second direction of the second source/drain region.

11. The semiconductor device of claim 10, wherein the first width in the second direction of the first source/drain region is different from the second width in the second direction of the second source/drain region.

12. The semiconductor device of claim 9, wherein the first depth in the third direction of the first source/drain region is different from the second depth in the third direction of the second source/drain region.

13. The semiconductor device of claim 9, wherein a sixth width in the first direction of the third source/drain region is greater than a fourth width in the first direction of the first source/drain region and a fifth width in the first direction of the second source/drain region.

14. The semiconductor device of claim 9, wherein an upper surface of the first source/drain region and an upper surface of the second source/drain region are convex.

15. The semiconductor device of claim 9, wherein an upper surface of the third source/drain region is concave.

16. A semiconductor device comprising:

a substrate comprising a first region and a second region;

a first gate electrode extending in a first direction on the first region;

a second gate electrode extending in the first direction on the first region and being separated from the first gate electrode in a second direction perpendicular to the first direction;

a third gate electrode extending in the first direction on the second region and being separated from the second gate electrode in the second direction;

a fourth gate electrode extending in the first direction on the second region and being separated from the third gate electrode in the second direction;

a plurality of fin active patterns extending in the second direction and spaced apart from each other in the first direction;

a first source drain region in the first region between the first and second gate electrodes intersecting one of the plurality of fin active patterns and having a first depth in a third direction perpendicular to the first and second directions;

a second source/drain region in the second region between the third and fourth gate electrodes intersecting the one of the plurality of fin active patterns and having a second depth in the third direction; and

a third source/drain region in the first and second regions between the second and third gate electrodes intersecting the one of the plurality of fin active patterns and having a third depth in the third direction,

wherein the third depth is greater than the first depth and the second depth.

17. The semiconductor device of claim 16, wherein the plurality of fin active patterns comprise:

a first fin active pattern extending in the second direction and intersecting the second and third gate electrodes;

a second fin active pattern extending in the second direction, being separated from the first fin active pattern in the first direction, and intersecting the first through fourth gate electrodes;

a third fin active pattern extending in the second direction, being separated from the second fin active pattern in the first direction, and intersecting the first and second gate electrodes;

a fourth fin active pattern extending in the second direction, being separated from the third fin active pattern in the second direction, and intersecting the third and fourth gate electrodes; and

a fifth fin active pattern extending in the second direction, being separated from the third and fourth fin active patterns in the first direction, and intersecting the first through fourth gate electrodes.

18. The semiconductor device of claim 16, wherein the first depth in the third direction of the first source/drain region is different from the second depth in the third direction of the second source/drain region.

19. The semiconductor device of claim 16, wherein a third width in the second direction of the third source/drain region is greater than a first width in the second direction of the first source/drain region and a second width in the second direction of the second source/drain region.

20. The semiconductor device of claim 16, wherein a sixth width in the first direction of the third source/drain region is greater than a fourth width in the first direction of the first source/drain region and a fifth width in the first direction of the second source/drain region.