High power semiconductor device
First Claim
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1. A high power semiconductor device comprising:
- a substrate;
a channel layer formed on the substrate and comprising a first region, a second region, and a third region;
a first barrier layer formed on the first region of the channel layer;
a first cap layer having a first conductivity type and formed on the first barrier layer;
a first electrode formed on the first barrier layer;
a second electrode formed on the first cap layer;
a second barrier layer formed on the second region of the channel layer;
a second cap layer having the first conductivity type and formed on the second barrier layer;
a third electrode formed on the second barrier layer;
a fourth electrode formed on the second cap layer;
a trench comprising a bottom wall and being disposed between the first barrier layer and the second barrier layer, wherein the trench exposes the third region of the channel layer; and
a connecting portion covering the bottom wall of the trench, electrically connected with the second electrode and the fourth electrode, and forming a schottky contact with the third region of the channel layer.
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Abstract
This application provides a high power semiconductor device, which is characterized by forming two diodes connected in parallel and a schottky contact on a channel layer to lower the turn-on voltage and turn-on resistance of the high power semiconductor device at the same time and to enhance the breakdown voltage.
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Citations
12 Claims
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1. A high power semiconductor device comprising:
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a substrate; a channel layer formed on the substrate and comprising a first region, a second region, and a third region; a first barrier layer formed on the first region of the channel layer; a first cap layer having a first conductivity type and formed on the first barrier layer; a first electrode formed on the first barrier layer; a second electrode formed on the first cap layer; a second barrier layer formed on the second region of the channel layer; a second cap layer having the first conductivity type and formed on the second barrier layer; a third electrode formed on the second barrier layer; a fourth electrode formed on the second cap layer; a trench comprising a bottom wall and being disposed between the first barrier layer and the second barrier layer, wherein the trench exposes the third region of the channel layer; and a connecting portion covering the bottom wall of the trench, electrically connected with the second electrode and the fourth electrode, and forming a schottky contact with the third region of the channel layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A high power semiconductor device comprising:
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a substrate; a first PIN diode structure disposed on the substrate; a second PIN diode structure disposed on the substrate; and a schottky-interface structure disposed on the substrate and between the first PIN diode structure and the second PIN diode structure, wherein the first PIN diode structure, the second PIN diode structure, and the schottky-interface structure are electrically connected with one another in parallel.
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11. A high power semiconductor device comprising:
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a substrate; a channel layer disposed on the substrate; a first semiconductor gate structure disposed on the channel layer; a metal-insulator-semiconductor gate structure disposed on the channel layer and having a recess; and a second semiconductor gate structure disposed on the channel layer; wherein the first semiconductor gate structure, the metal-insulator-semiconductor gate structure, and the second semiconductor gate structure are electrically connected with one another in parallel. - View Dependent Claims (12)
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Specification