Inverting buck-boost converter drive circuit and method

• US 10,122,279 B2
• Filed: 05/11/2017
• Issued: 11/06/2018
• Est. Priority Date: 10/24/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics Shenzhen R&D Co Ltd (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Shenzhen R&D Co Ltd (STMicroelectronics NV)
• Inventors: Zhang, Hai Bo, Huang, Jerry
• Primary Examiner(s): Pham, Emily P
• Assistant Examiner(s): Ahmad, Shahzeb K
• Application Number:
  US15/592,757
• Publication Number:
  US 20170250609A1
• Time in Patent Office: 544 Days
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0072 Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A driver circuit includes a high-side power transistor having a source-drain path coupled between a first node and a second node and a low-side power transistor having a source-drain path coupled between the second node and a third node. A high-side drive circuit, having an input configured to receive a drive signal, includes an output configured to drive a control terminal of said high-side power transistor. The high-side drive circuit is configured to operate as a capacitive driver. A low-side drive circuit, having an input configured to receive a complement drive signal, includes an output configured to drive a control terminal of said low-side power transistor. The low-side drive circuit is configured to operate as a level-shifting driver.

Claims

1. A circuit, comprising:

a power transistor having a drain terminal coupled to a input node and a source terminal coupled to an output node;

a drive circuit having an input configured to receive a drive signal and an output configured to output a first control signal;

a first capacitor having a first terminal coupled to receive the first control signal from the drive circuit and a second terminal configured to generate a first boosted control signal at a first intermediate node;

a diode having an anode coupled to the input node and a cathode coupled to the first intermediate node;

a circuit path configured to apply the first boosted control signal from the first intermediate node to a gate terminal of the power transistor;

an inverter circuit configured to invert the first control signal and generate a second control signal;

a second capacitor having a first terminal coupled to receive the second control signal from the inverter circuit and a second terminal configured to generate a second boosted control signal at a second intermediate node; and

a first transistor having a gate terminal coupled to receive the second boosted control signal from the second intermediate node, a drain terminal directly connected to the gate of the power transistor and a source terminal directly connected to the source terminal of the power transistor.

2. The circuit of claim 1, wherein the drive circuit comprises a further inverter circuit having a second transistor coupled between the input node and the output of the drive circuit and a third transistor coupled between the output of the drive circuit and a ground reference node.

3. The circuit of claim 2, wherein the second and third transistors form a logic inverter circuit.

4. The circuit of claim 1, wherein the circuit path coupling the first intermediate node to the gate terminal of the power transistor comprises a switch circuit operable to selectively connect the intermediate node to the gate terminal of the power transistor.

5. The circuit of claim 4, wherein the switch circuit comprises a fourth transistor having a source terminal coupled to the first intermediate node and a drain terminal coupled to the gate of the power transistor.

6. The circuit of claim 5, wherein a gate terminal of the fourth transistor is coupled to the input node.

7. The circuit of claim 1, further comprising a clamp diode coupled between the gate terminal of said first transistor and the source terminal of the power transistor.

8. The circuit of claim 7, further comprising a resistor coupled in parallel with the clamp diode.

9. The circuit of claim 1, further comprising a resistor coupled between the gate terminal and source terminal of the power transistor.

10. The circuit of claim 1, wherein said input node is configured to receive a power supply voltage.

11. The circuit of claim 1, wherein said output node is coupled to a load.

12. The circuit of claim 11, wherein the load is inductive.

13. A circuit, comprising:

a power transistor having a drain terminal coupled to an input node and a source terminal coupled to an output node;

a drive circuit having an input configured to receive a drive signal and an output configured to output a first control signal;

an inverter circuit configured to invert the first control signal and generate a second control signal;

a first capacitor having a first terminal coupled to receive the first control signal from the drive circuit and a second terminal configured to generate a first boosted control signal for application to a gate of said power transistor;

a first transistor having a drain terminal directly connected to the gate of the power transistor and a source terminal directly connected to the source terminal of the power transistor, said first transistor having a gate terminal; and

a second capacitor having a first terminal coupled to receive the second control signal and a second terminal configured to generate a second boosted control signal for application to the gate terminal of the first transistor.

14. The circuit of claim 13, further comprising:

a diode having an anode coupled to the input node and a cathode coupled to the second terminal of the first capacitor; and

a switch circuit operable to selectively connect the second terminal of the first capacitor to the gate terminal of the power transistor.

15. The circuit of claim 14, wherein the switch circuit comprises a second transistor having a source terminal coupled to the second terminal of the first capacitor and a drain terminal coupled to the gate of the power transistor.

16. The circuit of claim 15, wherein a gate terminal of the second transistor is coupled to the input node.

17. The circuit of claim 15, wherein a voltage at the input node is applied to a gate terminal of the second transistor.

18. The circuit of claim 13, wherein the drive circuit comprises an inverter circuit.

19. The circuit of claim 13, further comprising a clamp diode coupled between the gate terminal of said first transistor and the source terminal of the power transistor.

20. The circuit of claim 19, further comprising a resistor coupled in parallel with the clamp diode.

21. The circuit of claim 13, further comprising a resistor coupled between the gate terminal and source terminal of the power transistor.

22. A circuit, comprising:

a power transistor having a drain terminal connected to an input node, a source terminal connected to an output node, and a gate terminal;

a drive circuit configured to generate a first control signal and a second control signal that is a logical inversion of the first control signal;

a first boot capacitor configured to receive the first control signal and generate a first boosted control signal that is applied to the gate terminal of said power transistor;

a first transistor having a drain terminal connected to the gate of the power transistor, a source terminal connected to the source terminal of the power transistor, and a gate terminal; and

a second boot capacitor configured to receive the second control signal and generate a second boosted control signal that is applied to the gate terminal of said first transistor.

23. The circuit of claim 22, further comprising a switching circuit connected in series with the first boot capacitor and configured to selectively apply the first boosted control signal to the gate terminal of said power transistor.

24. The circuit of claim 23, further comprising:

a diode having an anode connected to the input node and a cathode connected to an intermediate node where the first boot capacitor is connected in series with the switching circuit.

25. The circuit of claim 22, wherein the switching circuit comprises a second transistor having a source terminal connected to the intermediate node and a drain terminal connected to the gate of the power transistor.

26. The circuit of claim 22, further comprising a clamp diode connected between the gate terminal of said first transistor and the source terminal of the power transistor.

27. The circuit of claim 26, further comprising a resistor connected in parallel with the clamp diode.

28. The circuit of claim 22, further comprising a resistor connected between the gate terminal of the power transistor and source terminal of the power transistor.