Programmable logic device and semiconductor device

• US 10,122,364 B2
• Filed: 05/05/2016
• Issued: 11/06/2018
• Est. Priority Date: 05/25/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ikeda, Takayuki, Kurokawa, Yoshiyuki
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US15/146,981
• Publication Number:
  US 20160322975A1
• Time in Patent Office: 915 Days
• Field of Search: None
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

Provided is a programmable logic device that includes logic elements arranged in a plurality of columns. Wirings connecting logic elements are arranged between the plurality of columns. Switch circuits that control electrical connections between the wirings and the logic elements are also arranged between the plurality of columns. Each of the switch circuit selects an electrical connection between one of the wirings and an input terminal of one of the logic elements in accordance with configuration data.

Claims

1. A programmable logic device comprising:

a plurality of first logic elements arranged in a first column;

a plurality of second logic elements arranged in a second column;

a plurality of third logic elements arranged in a third column parallel to the first column and the second column, wherein the second column is positioned between the first column and the third column;

a plurality of first wirings arranged between the first column and the second column, wherein the plurality of first wirings are electrically connected to corresponding first output terminals of the plurality of second logic elements;

a plurality of second wirings arranged between the second column and the third column, wherein the plurality of second wirings are electrically connected to corresponding second output terminals of the plurality of second logic elements;

a plurality of third wirings arranged both between the first column and the second column and between the second column and the third column via one of an upper end and a lower end of the second column, wherein the plurality of third wirings are electrically connected to corresponding first output terminals of the plurality of third logic elements; and

a plurality of switch circuits arranged between the first column and the second column, the plurality of switch circuits electrically connected to corresponding input terminals of the plurality of second logic elements and electrically connected to each of the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings.

2. The programmable logic device according to claim 1, wherein output terminals of the plurality of third logic elements are directly connected to the plurality of switch circuits between the first column and the second column through the plurality of third wirings.

3. The programmable logic device according to claim 1, wherein each of the plurality of switch circuits comprises a first switch and a second switch configured to be controlled by a configuration data input through the first switch.

4. The programmable logic device according to claim 3, wherein the first switch is a transistor comprising a metal oxide in a channel formation region.

5. The programmable logic device according to claim 4, wherein the metal oxide comprises at least one of indium, gallium, and zinc.

6. The programmable logic device according to claim 1, comprising:

a plurality of IO elements arranged in a fourth column, wherein the first column is positioned between the second column and the fourth column;

a plurality of fourth wirings arranged between the first column and the fourth column;

a plurality of fifth wirings arranged between the first column and the fourth column; and

a plurality of switches arranged between the first column and the fourth column,

wherein the plurality of fourth wirings are electrically connected to corresponding output terminal of the plurality of first logic elements,

wherein one of the plurality of switches is configured to electrically connect one of the plurality of fourth wirings to an input terminal of one of the plurality of IO elements, and

wherein the plurality of fifth wirings are electrically connected to corresponding output terminals of the plurality of IO elements.

7. The programmable logic device according to claim 1,

wherein each of the plurality of first logic elements, the plurality of second logic elements, and the plurality of third logic elements comprises a lookup table and a configuration memory operatively connected to the lookup table.

8. A programmable logic device comprising:

a plurality of first logic elements arranged in a first column;

a plurality of second logic elements arranged in a second column;

a plurality of third logic elements arranged in a third column parallel to the first column and the second column, wherein the second column is positioned between the first column and the third column;

a plurality of fourth logic elements arranged in a fourth column parallel to the first column, the second column, and the third column, wherein the third column is positioned between the second column and the fourth column

a plurality of first wirings arranged between the first column and the second column, wherein the plurality of first wirings are electrically connected to corresponding first output terminals of the plurality of second logic elements;

a plurality of second wirings arranged between the second column and the third column, wherein the plurality of second wirings are electrically connected to corresponding second output terminals of the plurality of second logic elements;

a plurality of third wirings arranged both between the first column and the second column and between the second column and the third column via one of an upper end and a lower end of the second column, wherein the plurality of third wirings are electrically connected to corresponding first output terminals of the plurality of third logic elements;

a plurality of fourth wirings arranged both between the second column and the third column and between the third column and the fourth column via one of an upper end and a lower end of the third column, wherein the plurality of fourth wirings are electrically connected to corresponding first output terminals of the plurality of fourth logic elements; and

a plurality of switch circuits arranged between the first column and the second column, the plurality of switch circuits electrically connected to corresponding input terminals of the plurality of second logic elements and electrically connected to each of the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings.

9. The programmable logic device according to claim 8, wherein output terminals of the plurality of third logic elements are directly connected to the plurality of switch circuits between the first column and the second column through the plurality of third wirings.

10. The programmable logic device according to claim 8, wherein each of the plurality of switch circuits comprises a first switch and a second switch configured to be controlled by a configuration data input through the first switch.

11. The programmable logic device according to claim 10, wherein the first switch is a transistor comprising a metal oxide in a channel formation region.

12. The programmable logic device according to claim 11, wherein the metal oxide comprises at least one of indium, gallium, and zinc.

13. The programmable logic device according to claim 8, comprising:

a plurality of IO elements arranged in a fifth column, wherein the first column is positioned between the second column and the fifth column;

a plurality of fourth wirings arranged between the first column and the fifth column;

a plurality of fifth wirings arranged between the first column and the fifth column; and

a plurality of switches arranged between the first column and the fifth column,

wherein the plurality of fourth wirings are electrically connected to corresponding output terminal of the plurality of first logic elements,

wherein one of the plurality of switches is configured to electrically connect one of the plurality of fourth wirings to an input terminal of one of the plurality of IO elements, and

wherein the plurality of fifth wirings are electrically connected to corresponding output terminals of the plurality of IO elements.

14. The programmable logic device according to claim 8,

wherein each of the plurality of first logic elements, the plurality of second logic elements, and the plurality of third logic elements comprises a lookup table and a configuration memory operatively connected to the lookup table.

15. The programmable logic device according to claim 8,

wherein the plurality of third wirings are arranged both between the first column and the second column and between the second column and the third column via the upper end of the second column, and

wherein the plurality of fourth wirings are arranged both between the second column and the third column and between the third column and the fourth column via the lower end of the third column.