Isolated phase shifted DC to DC converter with frequency synthesizer to reconstruct primary clock

• US 10,122,367 B1
• Filed: 09/22/2017
• Issued: 11/06/2018
• Est. Priority Date: 09/22/2017
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Albertini, Pierluigi, Granato, Maurizio, Massolini, Roberto Giampiero, Frattini, Giovanni
• Primary Examiner(s): Sterrett, Jeffrey
• Application Number:
  US15/712,239
• Time in Patent Office: 410 Days
• Field of Search: 363 47, 363 89, 363 98
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/33584 Bidirectional converters
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00

Abstract

Disclosed examples include isolated phase shifted dual active bridge DC to DC converters with a first bridge circuit operative according to a primary side clock signal to provide a primary voltage signal to a transformer primary winding, a second bridge circuit operative according to a secondary side clock signal to convert a secondary voltage signal from a transformer secondary winding to provide an output voltage signal, and a secondary side control circuit that alternately operates in a first mode to regulate the output voltage signal by controlling a phase shift angle between switching transitions of secondary side switching control signals and switching transitions of the secondary side clock signal, and a second mode to discontinue the secondary side switching control signals and synchronize the secondary side clock signal to transitions in the secondary voltage signal while the secondary side switching control signals are discontinued.

Claims

1. An isolated DC to DC converter, comprising:

a transformer, including a primary winding, and a secondary winding;

a first bridge circuit, including first bridge circuit input to receive an input signal, a first bridge circuit output coupled with the primary winding, and a plurality of primary switches individually coupled between the first bridge circuit input and the first bridge circuit output, the primary switches operative according to primary side switching control signals to provide a primary voltage signal to the first bridge circuit output;

a second bridge circuit, including a second bridge circuit input coupled to receive a secondary voltage signal from the secondary winding, a second bridge circuit output, and a plurality of secondary switches individually coupled between the second bridge circuit input and the second bridge circuit output, the secondary switches operative according to secondary side switching control signals to provide an output voltage signal at the second bridge circuit output;

a primary side control circuit configured to provide the primary side switching control signals according to a primary side clock signal; and

a secondary side control circuit configured to provide the secondary side switching control signals to regulate the output voltage signal by controlling a phase shift angle between switching transitions of the secondary side switching control signals and switching transitions of a secondary side clock signal, the secondary side control circuit including;

an interrupt circuit configured to selectively discontinue the secondary side switching control signals, and

a frequency synthesizer circuit configured to synchronize the secondary side clock signal to transitions in the secondary voltage signal while the secondary side switching control signals are discontinued.

2. The isolated DC to DC converter of claim 1, wherein the primary side control circuit includes:

a primary side driver circuit, including a plurality of outputs to provide the primary side switching control signals; and

a primary side timing circuit to provide the primary side clock signal to the primary side driver circuit to control timing of the primary side switching control signals.

3. The isolated DC to DC converter of claim 1, wherein the secondary side control circuit includes:

an analog front end circuit, including an input coupled to receive the secondary voltage signal from the secondary winding, a level shifting circuit, a filter circuit, and an output to provide a level shifted voltage signal according to the secondary voltage signal; and

a clock recovery circuit, including an input coupled with the output of the analog front end circuit to receive the level shifted voltage signal, and an output coupled with an input of the frequency synthesizer circuit to provide a recovered clock signal including transitions corresponding to the transitions in the secondary voltage signal.

4. The isolated DC to DC converter of claim 3, wherein the secondary side control circuit includes:

a delay circuit, including a first input to receive the secondary side clock signal, a second input to receive a control output signal to set the phase shift angle, and an output to provide a delay clock signal including transitions delayed by the phase shift angle from the switching transitions of the secondary side clock signal;

a secondary side driver circuit, including an input coupled with the output of the delay circuit to receive the delay clock signal, and a plurality of outputs to provide the secondary side switching control signals having switching transitions corresponding to the transitions of the delay clock signal; and

a voltage control circuit, including an output coupled with the second input of the delay circuit to provide the control output signal to set the phase shift angle according to the output voltage signal and a setpoint signal.

5. The isolated DC to DC converter of claim 4, wherein the interrupt circuit includes:

a counter with an input coupled to receive the secondary side clock signal;

a first output to provide an interrupt signal in a first state to cause the secondary side driver circuit to selectively discontinue the secondary side switching control signals in response to the counter counting an integer number N cycles of the secondary side clock signal, N being greater than or equal to 1; and

a second output to provide an enable signal in a first state to cause the frequency synthesizer circuit to synchronize the secondary side clock signal to transitions in the secondary voltage signal while the interrupt signal is in the first state.

6. The isolated DC to DC converter of claim 5,

wherein the first output of the interrupt circuit is configured to provide the interrupt signal in the first state for an integer number M cycles of the secondary side clock signal, and then to provide the interrupt signal in a different second state to cause the secondary side driver circuit to resume the secondary side switching control signals while the counter counts another N cycles of the secondary side clock signal, M being greater than 1, and

wherein the second output of the interrupt circuit is configured to provide the enable signal in the first state for M cycles of the secondary side clock signal to cause the frequency synthesizer circuit to synchronize the secondary side clock signal to transitions in the secondary voltage signal while the interrupt signal is in the first state, and then to provide the enable signal in a different second state to cause the cause the frequency synthesizer circuit to maintain the secondary side clock signal at a constant frequency and phase while the interrupt signal is in the second state.

7. The isolated DC to DC converter of claim 5, wherein the frequency synthesizer circuit includes:

a phase locked loop (PLL), including;

a PLL output to provide the secondary side clock signal,

a first input coupled to receive the recovered clock signal from the output of the clock recovery circuit,

a second input coupled with the PLL output to receive a feedback clock signal based on the secondary side clock signal, and

a third input coupled with the second output of the interrupt circuit to receive the enable signal,

wherein the PLL is operative when the enable signal is in the first state to synchronize the switching transitions of the secondary side clock signal to transitions in the recovered clock signal, and wherein the PLL is operative when the enable signal is in the second state to maintain the secondary side clock signal at a constant frequency and phase.

8. The isolated DC to DC converter of claim 5, wherein N is greater than or equal to 100.

9. The isolated DC to DC converter of claim 1, wherein the secondary side control circuit includes:

a delay circuit, including a first input to receive the secondary side clock signal, a second input to receive a control output signal to set the phase shift angle, and an output to provide a delay clock signal including transitions delayed by the phase shift angle from the switching transitions of the secondary side clock signal;

a secondary side driver circuit, including an input coupled with the output of the delay circuit to receive the delay clock signal, and a plurality of outputs to provide the secondary side switching control signals having switching transitions corresponding to the transitions of the delay clock signal; and

a voltage control circuit, including an output coupled with the second input of the delay circuit to provide the control output signal to set the phase shift angle according to the output voltage signal and a setpoint signal.

10. The isolated DC to DC converter of claim 1, wherein the interrupt circuit includes:

a counter with an input coupled to receive the secondary side clock signal;

a first output to provide an interrupt signal in a first state to selectively discontinue the secondary side switching control signals in response to the counter counting an integer number N cycles of the secondary side clock signal, N being greater than or equal to 1; and

a second output to provide an enable signal in a first state to cause the frequency synthesizer circuit to synchronize the secondary side clock signal to transitions in the secondary voltage signal while the interrupt signal is in the first state.

11. The isolated DC to DC converter of claim 10,

wherein the first output of the interrupt circuit is configured to provide the interrupt signal in the first state for an integer number M cycles of the secondary side clock signal, and then to provide the interrupt signal in a different second state to resume the secondary side switching control signals while the counter counts another N cycles of the secondary side clock signal, M being greater than 1, and

wherein the second output of the interrupt circuit is configured to provide the enable signal in the first state for M cycles of the secondary side clock signal to synchronize the secondary side clock signal to transitions in the secondary voltage signal while the interrupt signal is in the first state, and then to provide the enable signal in a different second state to maintain the secondary side clock signal at a constant frequency and phase while the interrupt signal is in the second state.

12. The isolated DC to DC converter of claim 10, wherein the frequency synthesizer circuit includes:

a phase locked loop (PLL), including;

a PLL output to provide the secondary side clock signal,

a first input coupled to receive a recovered clock signal including transitions corresponding to the transitions in the secondary voltage signal,

a second input coupled with the PLL output to receive a feedback clock signal based on the secondary side clock signal, and

a third input coupled with the second output of the interrupt circuit to receive the enable signal,

wherein the PLL is operative when the enable signal is in the first state to synchronize the switching transitions of the secondary side clock signal to transitions in the recovered clock signal, and wherein the PLL is operative when the enable signal is in the second state to maintain the secondary side clock signal at a constant frequency and phase.

13. The isolated DC to DC converter of claim 1,

wherein the first bridge circuit is a full bridge circuit, including four primary switches individually coupled between the first bridge circuit input and the first bridge circuit output;

and

wherein the second bridge circuit is a full bridge circuit, including four secondary switches individually coupled between the second bridge circuit input and the second bridge circuit output.

14. A phase shifted dual active bridge DC to DC converter, comprising:

a first bridge circuit configured to convert an input signal to provide a primary voltage signal to a primary winding of a transformer according to a primary side switching control signal;

a primary side control circuit configured to provide the primary side switching control signal according to a primary side clock signal;

a second bridge circuit configured to convert a secondary voltage signal from a secondary winding of the transformer to provide an output voltage signal according to a secondary side switching control signal;

a secondary side control circuit operative in a first mode to provide the secondary side switching control signal to regulate the output voltage signal by controlling a phase shift angle between switching transitions of the secondary side switching control signal and switching transitions of a secondary side clock signal, the secondary side control circuit operative in a second mode to discontinue the secondary side switching control signal, and to synchronize the secondary side clock signal to transitions in the secondary voltage signal while the secondary side switching control signal is discontinued.

15. The phase shifted dual active bridge DC to DC converter of claim 14, wherein the secondary side control circuit alternates between the first and second modes, wherein the secondary side control circuit operates in a first mode for an integer number N cycles of the secondary side clock signal, and wherein the secondary side control circuit operates in the second mode for an integer number M cycles of the secondary side clock signal, N and M being greater than 1.

16. The phase shifted dual active bridge DC to DC converter of claim 15, wherein N is greater than or equal to 100, and wherein M is 2.

17. The phase shifted dual active bridge DC to DC converter of claim 15, wherein the secondary side control circuit includes a phase locked loop (PLL), the PLL including:

a PLL output to provide the secondary side clock signal;

a first input coupled to receive a recovered clock signal that indicates the transitions in the secondary voltage signal;

a second input coupled with the PLL output to receive a feedback clock signal based on the secondary side clock signal; and

a third input coupled with a second output of an interrupt circuit to receive an enable signal;

wherein the PLL operates in the second mode when the enable signal is in a first state to synchronize the switching transitions of the secondary side clock signal to transitions in the recovered clock signal, and wherein the PLL operates in the first mode when the enable signal is in a second state to maintain the secondary side clock signal at a constant frequency and phase.

18. A method for operating a phase shifted dual active bridge DC to DC converter, the method comprising:

operating secondary switches of a dual active bridge DC to DC converter to convert a transformer secondary voltage signal to regulate a converter output voltage signal by controlling a phase shift angle between switching transitions of secondary side switching control signals and switching transitions of a secondary side clock signal;

discontinuing the secondary side switching control signals after an integer number N cycles of the secondary side clock signal, N being greater than 1;

synchronizing the secondary side clock signal to transitions in the transformer secondary voltage signal while the secondary side switching control signals are discontinued; and

resuming the secondary side switching control signals after synchronizing the secondary side clock signal to the transitions in the transformer secondary voltage signal.

19. The method of claim 18, comprising discontinuing the secondary side switching control signals for an integer number M cycles of the secondary side clock signal before resuming the secondary side switching control signals.

20. The method of claim 19, wherein N is greater than or equal to 100, and wherein M is 2.