Circuit board structure and manufacturing method thereof

• US 10,123,418 B1
• Filed: 02/23/2018
• Issued: 11/06/2018
• Est. Priority Date: 12/13/2017
• Status: Active Grant

• Current Assignee: Unimicron Technology Corporation
• Original Assignee: Unimicron Technology Corporation
• Inventors: Lin, Wei-Ti, Chien, Chun-Hsien, Chen, Fu-Yang
• Primary Examiner(s): Norris, Jeremy C
• Application Number:
  US15/903,049
• Time in Patent Office: 256 Days
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2027/065 Mounting on printed circuit boards
• CPC Class Codes: H01F 27/06 Mounting, supporting or suspending transformers, reactors or choke coils not being of the signal type
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/165 incorporating printed inductors
• CPC Class Codes: H05K 1/188 manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
• CPC Class Codes: H05K 2201/09563 Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 3/0011 Working of insulating substrates or insulating layers
• CPC Class Codes: H05K 3/10 in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

A circuit board structure including an insulating layer, first and second dielectric layers, and first and second inductors is provided. The insulating layer includes a first surface, a second surface, and a first conductive through hole. The first dielectric layer is disposed on the first surface. The first inductor is disposed on the first surface and includes a first conductive coil in a solenoid form penetrating the first dielectric layer and a first magnetic flux axis of which the direction is substantially parallel to the first surface. The second dielectric layer is disposed on the second surface. The second inductor is disposed on the second surface and includes a second conductive coil in a solenoid form penetrating the second dielectric layer and a second magnetic flux axis of which the direction is substantially parallel to the second surface. A manufacturing method of a circuit board structure is provided.

Claims

1. A circuit board structure, comprising:

an insulating layer, comprising a first conductive through hole, a first surface, and a second surface opposite to the first surface, the first conductive through hole penetrating the insulating layer to connect the first surface and the second surface;

a first dielectric layer, disposed on the first surface;

a first inductor, disposed on the first surface of the insulating layer and electrically connecting the first conductive through hole, the first inductor comprising a first conductive coil and a first magnetic flux axis, wherein the first conductive coil in a solenoid form penetrates the first dielectric layer, and a direction of the first magnetic flux axis is substantially parallel to the first surface;

a second dielectric layer disposed on the second surface; and

a second inductor, located on the second surface of the insulating layer and electrically connecting the first conductive through hole, the second inductor comprising a second conductive coil and a second magnetic flux axis, wherein the second conductive coil in a solenoid form penetrates the second dielectric layer, and a direction of the second magnetic flux axis is substantially parallel to the second surface.

2. The circuit board structure of claim 1, wherein the insulating layer comprises a core layer.

3. The circuit board structure of claim 2, wherein a material of the core layer is different from materials of the first dielectric layer and the second dielectric layer, the material of the core layer comprises a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, an insulator-on-silicon substrate, or a polyimide glass fiber composite substrate.

4. The circuit board structure of claim 1, wherein a material of the insulating layer is identical to materials of the first dielectric layer and the second dielectric layer.

5. The circuit board structure of claim 1, wherein the first conductive coil comprises:

a plurality of first upper coil patterns, arranged in parallel with one another and disposed on the first surface of the insulating layer;

a plurality of first lower coil patterns, arranged in parallel with one another and disposed on the first dielectric layer; and

a plurality of first conductive blind holes, penetrating the first dielectric layer to electrically connect the plurality of first upper coil patterns and the plurality of first lower coil patterns.

6. The circuit board structure of claim 1, wherein the second conductive coil comprises:

a plurality of second upper coil patterns, arranged in parallel with one another and disposed on the second surface of the insulating layer;

a plurality of second lower coil patterns, arranged in parallel with one another and disposed on the second dielectric layer; and

a plurality of second conductive blind holes, penetrating the second dielectric layer to electrically connect the plurality of second upper coil patterns and the plurality of second lower coil patterns.

7. The circuit board structure of claim 1, wherein the first inductor on the insulating layer at least partially overlaps the second inductor in an orthogonal projection direction.

8. The circuit board structure of claim 1, wherein a minimum vertical distance from the first inductor to the second inductor is less than or equal to 100 μ

m.

9. The circuit board structure of claim 1, further comprising a third inductor located on one side of the first inductor and the second inductor and electrically coupled to the first inductor or the second inductor, the third inductor comprising a third conductive coil and a third magnetic flux axis, wherein the third conductive coil in a solenoid form penetrates the insulating layer, and a direction of the third magnetic flux axis is substantially parallel to the first surface.

10. The circuit board structure of claim 9, wherein the third conductive coil comprises:

a plurality of third upper coil patterns, disposed on the first surface of the insulating layer;

a plurality of third lower coil patterns, disposed on the second surface of the insulating layer; and

a plurality of third conductive through holes, penetrating the insulating layer to electrically connect the plurality of third upper coil patterns and the plurality of third lower coil patterns.

11. The circuit board structure of claim 9, wherein the third conductive coil comprises:

a plurality of third upper coil patterns is disposed on the first dielectric layer, a plurality of third lower coil patterns is disposed on the second dielectric layer, and a plurality of third conductive though holes penetrates the insulating layer, the first dielectric layer, and the second dielectric layer to electrically connect the plurality of third upper coil patterns and the plurality of third lower coil patterns.

12. The circuit board structure of claim 9, wherein a minimum horizontal distance from the third inductor to the first inductor or the second inductor is less than or equal to 100 μ

m.

13. The circuit board structure of claim 10, wherein each of the plurality of third conductive through holes comprises a solid conductive post, a hollow conductive through hole, or an X-type conductive through hole.

14. A manufacturing method of a circuit board structure, comprising:

providing an insulating layer comprising a first conductive through hole, a first surface, and a second surface opposite to the first surface, the first conductive through hole penetrating the insulating layer to connect the first surface and the second surface;

forming a plurality of first upper coil patterns parallel to one another on the first surface of the insulating layer;

forming a plurality of second upper coil patterns parallel to one another on the second surface of the insulating layer;

forming a first dielectric layer on the plurality of first upper coil patterns;

forming a second dielectric layer on the plurality of second upper coil patterns;

forming a plurality of first conductive blind holes penetrating the first dielectric layer;

forming a plurality of second conductive blind holes penetrating the second dielectric layer;

forming a plurality of first lower coil patterns parallel to one another on the first dielectric layer, wherein the plurality of first lower coil patterns is electrically connected to the plurality of first upper coil patterns via the plurality of first conductive blind holes, and the plurality of first upper coil patterns, the plurality of first conductive blind holes, and the plurality of first lower coil patterns constitute a first inductor; and

forming a plurality of second lower coil patterns parallel to one another on the second dielectric layer, wherein the plurality of second lower coil patterns is electrically connected to the plurality of second upper coil patterns via the plurality of second conductive through holes, and the plurality of second upper coil patterns, the plurality of second conductive blind holes, and the plurality of second lower coil patterns constitute a second inductor.

15. The manufacturing method of the circuit board structure of claim 14, wherein an extension direction of the plurality of first upper coil patterns is different from an extension direction of the plurality of first lower coil patterns, and an extension direction of the plurality of second upper coil patterns is different from an extension direction of the plurality of second lower coil patterns.

16. The manufacturing method of the circuit board structure of claim 14, wherein the first inductor on the insulating layer at least partially overlaps the second inductor in an orthogonal projection direction.

17. The manufacturing method of the circuit board structure of claim 14, wherein a minimum vertical distance from the first inductor to the second inductor is less than or equal to 100 μ

m.

18. The manufacturing method of the circuit board structure of claim 14, further comprising:

forming a plurality of third conductive through holes penetrating the insulating layer; and

respectively forming a plurality of third upper coil patterns and a plurality of third lower coil patterns on the first surface and the second surface of the insulating layer, wherein the plurality of third lower coil patterns is electrically connected to the plurality of third upper coil patterns via the plurality of third conductive through holes, and the plurality of third upper coil patterns, the plurality of third conductive through holes, and the plurality of third lower coil patterns constitute a third inductor.

19. The manufacturing method of the circuit board structure of claim 18, wherein a minimum horizontal distance from the third inductor to the first inductor or the second inductor is less than or equal to 100 μ

m.

20. The manufacturing method of the circuit board structure of claim 14, further comprising:

forming a plurality of third conductive through holes penetrating the insulating layer, the first dielectric layer and the second dielectric layer; and

respectively forming a plurality of third upper coil patterns and a plurality of third lower coil patterns on the first dielectric layer and the second dielectric layer, wherein the plurality of third lower coil patterns is electrically connected to the plurality of third upper coil patterns via the plurality of third conductive through holes, and the plurality of third upper coil patterns, the plurality of third conductive through holes, and the plurality of third lower coil patterns constitute a third inductor.