Low power asynchronous GPS baseband processor

• US 10,126,428 B2
• Filed: 02/25/2013
• Issued: 11/13/2018
• Est. Priority Date: 02/23/2012
• Status: Active Grant

• Current Assignee: Cornell University
• Original Assignee: Cornell University
• Inventors: Manohar, Rajit, Tang, Benjamin, Longfield, Stephen, Bhave, Sunil A.
• Primary Examiner(s): Phan, Dao L
• Application Number:
  US14/380,700
• Publication Number:
  US 20150022397A1
• Time in Patent Office: 2,087 Days
• Field of Search: 34235763, 34235768, 34235769, 34235777, 34235778, 701467, 701468
• CPC Class Codes: G01S 19/24 Acquisition or tracking or demodulation of signals transmitted by the system synchronisation aspects of direct sequence spread spectrum modulation H04B1/7073
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain

Abstract

Asynchronous Global Positioning System (GPS) baseband processor architectures with a focus on minimizing power consumption. All subsystems run at their natural frequency without clocking and all signal processing is done on-the-fly.

Claims

1. A asynchronous global positioning system (GPS) channel baseband processor comprising:

a number of channel units, one unit for each channel from a number of channels, each channel unit including an asynchronous acquisition subsystem configured to obtain code offset and Doppler frequency estimates;

said asynchronous acquisition subsystem receiving input from an RF front end;

an asynchronous tracking subsystem configured to track deviations in the code offset and Doppler frequency;

said asynchronous tracking subsystem receiving data for code offset and Doppler frequency estimates;

each channel unit including an asynchronous downsampling component receiving an output from the asynchronous tracking subsystem and configured for downsampling the output of the asynchronous tracking subsystem down to a navigation data sampling rate; and

each channel unit including an asynchronous decoding subsystem receiving output from the asynchronous downsampling component and providing GPS satellite time and code start time information;

said asynchronous decoding subsystem processing signals of a third frequency;

wherein said asynchronous acquisition subsystem, said asynchronous tracking subsystem, said asynchronous downsampling component and said asynchronous decoding subsystem operate without clocking,

wherein the number of channels are configured to share the asynchronous tracking subsystem.

2. The asynchronous GPS channel baseband processor of claim 1 wherein the asynchronous acquisition subsystem comprises:

two asynchronous numerical controlled oscillators (NCO), a carrier NCO and a code NCO;

the two asynchronous NCOs receive inputs from the RF front end; and

the code NCO controlling a chipping rate of a code replica generator; and

accumulators;

the accumulators receiving output from the carrier NCO and the code replica generator and producing, as outputs in phase and quadrature accumulations.

3. The asynchronous GPS channel baseband processor of claim 2 wherein each channel unit comprises:

an asynchronous delay locked loop (DLL) component receiving in phase and quadrature accumulations, late in phase and quadrature accumulations and early in phase and quadrature accumulations from the accumulators;

late in phase and quadrature accumulations being obtained by delaying a pseudo random noise code by one half of a chip; and

early in phase and quadrature accumulation being obtained by advancing the pseudo random noise code by one half of a chip;

the asynchronous DLL component being configured to update a chipping rate;

an asynchronous frequency locked loop (FLL) component receiving in phase and quadrature accumulations from the accumulators;

the asynchronous FLL component configured to obtain a more accurate estimate of the Doppler frequency; and

an asynchronous phase lock loop (PLL) component receiving in phase and quadrature accumulations from the accumulators;

the asynchronous PLL component configured to track the Doppler frequency.

4. The asynchronous GPS channel baseband processor of claim 3 wherein the asynchronous DLL component comprises:

a delay error estimator; and

an updated chipping rate estimator.

5. The asynchronous GPS channel baseband processor of claim 4 wherein the delay error estimator provides a delay error estimate in units of chips given by

6. The asynchronous GPS channel baseband processor of claim 3 wherein the asynchronous FLL component comprises:

a determinator of a rotation angle of a prompt in-phase and quadrature accumulations'"'"' phasor, the Doppler frequency being proportional to a rate of rotation of the prompt in-phase and quadrature accumulations'"'"' phasor.

7. The asynchronous GPS channel baseband processor of claim 6 wherein the determinator of the rotation angle provides the rotation angle of the prompt in-phase and quadrature accumulations'"'"' phasor given by

8. The asynchronous GPS channel baseband processor of claim 3 wherein the asynchronous PLL component comprises a discriminator that minimizes a phasor angle between a quadrature accumulation vector and an in-phase accumulation vector at an end of an n^th accumulation period.

9. The asynchronous GPS channel baseband processor of claim 8 wherein the discriminator provides a minimum phasor angle given by

10. The asynchronous GPS channel baseband processor of claim 3 wherein calculations are performed using fixed point arithmetic.

11. The asynchronous GPS channel baseband processor of claim 2 wherein each accumulator comprises:

an accumulator for a reduced number of bits; and

an increment-decrement-dump (IDD) unit, the IDD unit handling a remaining number of bits.

12. The asynchronous GPS channel baseband processor of claim 2 wherein the accumulators provide prompt in phase and quadrature accumulations to a magnitude determinator;

said magnitude determinator providing a correlation power estimate;

said code offset and Doppler frequency estimates being acquired when the correlation power estimate is greater than a predetermined threshold.

13. The asynchronous GPS channel baseband processor of claim 12 wherein the correlation power estimate is given by I²+Q², where

14. The asynchronous GPS channel baseband processor of claim 2 wherein the asynchronous decoding subsystem comprises a code phase accumulator, the code phase accumulator providing a code start time;

the code start time (CST) being incremented, from an initial code start time, when the DLL updates, by a number of samples in a time lapsed during DLL updating.

15. The asynchronous GPS channel baseband processor of claim 14 wherein the initial code start time is given by

16. The asynchronous GPS channel baseband processor of claim 1 wherein said asynchronous acquisition subsystem, said asynchronous tracking subsystem, said asynchronous downsampling component and said asynchronous decoding subsystem operate at predetermined frequency ratios.

17. An asynchronous GPS channel baseband processor comprising:

a number of channel units, one unit for each channel from a number of channels;

each channel unit comprising;

an asynchronous acquisition subsystem configured to obtain code offset and Doppler frequency estimates;

said asynchronous acquisition subsystem receiving input from an RF front end;

said asynchronous acquisition subsystem processing signals of a first frequency;

an asynchronous downsampling component receiving an output from an asynchronous tracking subsystem and configured for downsampling the output of the asynchronous tracking subsystem down to a navigation data sampling rate; and

an asynchronous decoding subsystem receiving output from the asynchronous downsampling component and providing GPS satellite time and code start time information;

said asynchronous decoding subsystem processing signals of a third frequency;

wherein said asynchronous acquisition subsystem, said asynchronous tracking subsystem, said asynchronous downsampling component and said asynchronous decoding subsystem operate without clocking;

said asynchronous GPS channel baseband processor further comprising;

at least one arbitrated multiplexer receiving data for code offset and Doppler frequency estimates for each of the number of channels;

an asynchronous tracking subsystem configured to track the code offset and Doppler frequency;

said asynchronous tracking subsystem receiving data for code offset and Doppler frequency estimates for one channel from said at least one arbitrated multiplexer;

said asynchronous tracking subsystem processing signals of a second frequency; and

at least one arbitrated demultiplexer receiving the output from the asynchronous tracking subsystem and distributing the output to said one channel,

wherein the number of channels are configured to share the asynchronous tracking subsystem using said at least one arbitrated multiplexer and said at least one arbitrated demultiplexer.

18. The asynchronous GPS channel baseband processor of claim 17 wherein the GPS satellite time and code start time information for each channel is provided to an external process for navigation solution computation.

19. The asynchronous GPS channel baseband processor of claim 17 wherein the asynchronous acquisition subsystem comprises:

two asynchronous numerical controlled oscillators (NCO), a carrier NCO and a code NCO;

the two asynchronous NCOs receive inputs from the RF front end; and

the code NCO controlling a chipping rate of a code replica generator; and

accumulators;

the accumulators receiving output from the carrier NCO and the code replica generator and producing, as outputs in phase and quadrature accumulations.

20. The asynchronous GPS channel baseband processor of claim 19 wherein each channel unit comprises:

an asynchronous delay locked loop (DLL) component receiving in phase and quadrature accumulations, late in phase and quadrature accumulations and early in phase and quadrature accumulations from the accumulators;

late in phase and quadrature accumulations being obtained by delaying a pseudo random noise code by one half of a chip; and

early in phase and quadrature accumulation being obtained by advancing the pseudo random noise code by one half of a chip;

the asynchronous DLL component being configured to update a chipping rate;

an asynchronous frequency locked loop (FLL) component receiving in phase and quadrature accumulations from the accumulators;

the asynchronous FLL component configured to obtain a more accurate estimate of the Doppler frequency; and

an asynchronous phase lock loop (PLL) component receiving in phase and quadrature accumulations from the accumulators;

the asynchronous PLL component configured to track the Doppler frequency.

21. The asynchronous GPS channel baseband processor of claim 20 wherein calculations are performed using fixed point arithmetic.

22. The asynchronous GPS channel baseband processor of claim 17 further comprising:

at least another arbitrated multiplexer receiving prompt in phase and quadrature accumulations from the accumulators from each of the number of channels;

a magnitude determinator;

said magnitude determinator providing a correlation power estimate for one channel in the number of channels;

said code offset and Doppler frequency estimates being acquired when the correlation power estimate is greater than a predetermined threshold; and

at least another arbitrated demultiplexer receiving an output from the magnitude determinator and distributing the output from the magnitude determinator to said one channel.

23. The asynchronous GPS channel baseband processor of claim 22 wherein calculations are performed using fixed point arithmetic.

24. The asynchronous GPS channel baseband processor of claim 20 further comprising:

at least yet another arbitrated multiplexer receiving, when the asynchronous DLL component updates, a number of samples in a time lapsed during DLL updating, and code offset and Doppler frequency estimates from each of the number of channels;

a code phase accumulator, the code phase accumulator providing a code start time for one channel in the number of channels;

the code start time (CST) being incremented, from an initial code start time, when the DLL updates, by a number of samples in a time lapsed during DLL updating for said one channel; and

at least yet another arbitrated demultiplexer receiving the code start time from the code phase accumulator and distributing the code start time to said one channel.

25. The asynchronous GPS channel baseband processor of claim 24 wherein calculations are performed using fixed point arithmetic.