Method of managing power consumption within a multi-core microprocessor utilizing an inter-core state discovery process to identify a least power-conserving target core state of all of the cores that share the resource
First Claim
1. A method of managing power consumption within a multi-core microprocessor, the method comprising:
- issuing an operating-system instruction to transition a recipient core to a target core state associated with one or more settings that would affect a performance or power-consuming characteristic of the microprocessor;
implementing, by the recipient core, all settings associated with the target core state for the recipient core that would not affect resources shared with other cores;
determining, by the recipient core, whether the target core state is associated with one or more settings that would affect at least one performance or power consuming characteristic of at least one resource shared with one or more other resource-sharing cores;
in response to the determining operation, only when the target core state is associated with one or more settings that would affect at least one performance or power consuming characteristic of at least one resource shared with one or more other resource-sharing cores, determining, by the recipient core, a target multi-core state of the recipient and other resource-sharing cores, wherein the target multi-core state is only associated with one or more settings that match the settings of the recipient core'"'"'s target core state as much as possible without lowering a performance of any other resource-sharing core below the resource-sharing core'"'"'s own target core state; and
implementing, by the recipient core, the one or more settings associated with the target multi-core state.
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Accused Products
Abstract
A method is provided for managing power consumption within a multi-core microprocessor. An operating system issues an operating system instruction to transition a recipient core to a targeted power and/or performance state that is one of many possible states into which a microprocessor can place a core. Each core of the microprocessor has its own target state, and different cores may have different target states. After receiving the instruction, the recipient core implements any settings associated with its target core state that wouldn'"'"'t affect resources shared with other cores. The recipient core also initiates an inter-core discovery process to determine a target multi-core state of all the cores sharing the resource. The target multi-core state reflects one or more settings that match the settings of the recipient core'"'"'s target core state as much as possible without lowering a performance of any resource-sharing core below that core'"'"'s own target core state.
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Citations
18 Claims
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1. A method of managing power consumption within a multi-core microprocessor, the method comprising:
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issuing an operating-system instruction to transition a recipient core to a target core state associated with one or more settings that would affect a performance or power-consuming characteristic of the microprocessor; implementing, by the recipient core, all settings associated with the target core state for the recipient core that would not affect resources shared with other cores; determining, by the recipient core, whether the target core state is associated with one or more settings that would affect at least one performance or power consuming characteristic of at least one resource shared with one or more other resource-sharing cores; in response to the determining operation, only when the target core state is associated with one or more settings that would affect at least one performance or power consuming characteristic of at least one resource shared with one or more other resource-sharing cores, determining, by the recipient core, a target multi-core state of the recipient and other resource-sharing cores, wherein the target multi-core state is only associated with one or more settings that match the settings of the recipient core'"'"'s target core state as much as possible without lowering a performance of any other resource-sharing core below the resource-sharing core'"'"'s own target core state; and implementing, by the recipient core, the one or more settings associated with the target multi-core state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A multi-core microprocessor comprising:
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a plurality of cores each configured to execute an operating-system issued instruction to transition itself to a target core state associated with one or more settings that would affect a performance or power-consuming characteristic of the microprocessor, each of the cores transitioning by; implementing all settings associated with the target core state for the recipient core that would not affect resources shared with other cores; determining whether the target core state is associated with one or more settings that would affect at least one performance or power consuming characteristic of at least one resource shared with one or more other resource-sharing cores; in response to the determining operation, only when the target core state is associated with one or more settings that would affect at least one performance or power consuming characteristic of at least one resource shared with one or more other resource-sharing cores, determining a target multi-core state of the recipient and other resource-sharing cores, wherein the target multi-core state is only associated with one or more settings that match the settings of the recipient core'"'"'s target core state as much as possible without lowering a performance of any other resource-sharing core below the resource-sharing core'"'"'s own target core state; and implementing the one or more settings associated with the target multi-core state. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method of managing power consumption within a multi-core microprocessor, the method comprising:
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issuing an operating-system instruction to a recipient core to implement a target core state to the extent that the target core state does not conflict with any target core state of any other core that shares a resource that would be affected by the target core state; initiating, by the recipient core, an inter-core state discovery process to identify a least power-conserving target core state of all of the cores that share the resource; determining, by the recipient core, whether the target core state is associated with one or more settings that would affect at least one performance or power consuming characteristic of at least one resource shared with one or more other resource-sharing cores; in response to the determining operation, only when the least power-conserving core state of all the cores that share the resource is identified, implementing, by the recipient core, the least power-conserving core state for the recipient core.
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Specification