Efficient configuration of memory components

• US 10,126,968 B2
• Filed: 09/24/2015
• Issued: 11/13/2018
• Est. Priority Date: 09/24/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bialas, Jr., John S., Glancy, Stephen P., Sethuraman, Saravanan, Sloat, Jacob D.
• Primary Examiner(s): Bataille, Pierre Miche
• Application Number:
  US14/863,590
• Publication Number:
  US 20170090804A1
• Time in Patent Office: 1,146 Days
• Field of Search: 711105, 711170, 711154
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413

Abstract

In an example, a system includes a memory controller that includes a plurality of memory components. The system also includes a memory controller configured to receive a plurality of memory settings to be applied to the plurality of memory components. The memory controller is configured to, based on the received memory settings, transmit a first command to the plurality of memory components, the first command causing each memory component of the plurality of memory components to be configured to a first memory setting. The memory controller is configured to, based on the received memory settings, transmit a second command to a subset of the plurality of memory components after transmitting the first command, the second command causing each memory component of the subset to be configured to a second memory setting.

Claims

1. A method, comprising:

receiving, at a memory controller, a plurality of memory settings to be applied to a plurality of memory components;

based on the received memory settings, transmitting a first command to the plurality of memory components, the first command causing each memory component of the plurality of memory components to be configured to a first memory setting;

based on the received memory settings, transmitting a second command to a subset of the plurality of memory components after transmitting the first command, the second command causing each memory component of the subset to be configured to a second memory setting; and

comparing the plurality of memory settings to determine a number of memory components of a second subset of the plurality of memory components, wherein each memory component of the second subset is associated with the first memory setting, and wherein the first command is transmitted in response to the number of memory components of the second subset satisfying a threshold,

wherein to transmit the second command, the memory controller is further configured to transmit the second command to the subset while a memory component control mode is activated.

2. The method of claim 1, wherein each memory component of the subset is associated with a corresponding reference voltage setting that is within a voltage range, and the second memory setting comprises a particular reference voltage setting that is within the voltage range.

3. The method of claim 1, wherein the plurality of memory settings comprise a plurality of reference voltage settings.

4. The method of claim 1, wherein transmitting the second command comprises:

activating the memory component control mode; and

transmitting the second command to the subset while the memory component control mode is activated; and

deactivating the memory component control mode after transmitting the second command.

5. A system, comprising:

a memory comprising a plurality of memory components; and

a memory controller configured to;

receive a plurality of memory settings to be applied to the plurality of memory components;

based on the received memory settings, transmit a first command to the plurality of memory components, the first command causing each memory component of the plurality of memory components to be configured to a first memory setting; and

based on the received memory settings, transmit a second command to a subset of the plurality of memory components after transmitting the first command, the second command causing each memory component of the subset to be configured to a second memory setting;

wherein to transmit the second command, the memory controller is further configured to;

activate a memory component control mode;

transmit the second command to the subset while the memory component control mode is activated; and

deactivate the memory component control mode after transmitting the second command.

6. The system of claim 5, wherein the memory controller is further configured to:

compare the plurality of memory settings to determine a number of memory components of a second subset of the plurality of memory components, wherein each memory component of the second subset is associated with the first memory setting, and wherein the first command is transmitted in response to the number of memory components of the second subset satisfying a threshold.

7. The system of claim 6, wherein the threshold corresponds to a percentage of a total number of the plurality of memory components.

8. The system of claim 5, wherein the plurality of memory settings comprise a plurality of reference voltage settings.

9. The system of claim 5, wherein each memory component of the subset is associated with a corresponding reference voltage setting that is within a voltage range, and the second memory setting comprises a particular reference voltage setting that is within the voltage range.

10. The system of claim 5, wherein the first command comprises a global memory command configured to apply the first memory setting to each memory component of the plurality of memory components.

11. The system of claim 10, wherein the first command is a mode register set (MRS) command or a buffer control word (BCW) command.

12. The system of claim 5, wherein the second command comprises a memory component command configured to apply the second memory setting to one or more memory components of the plurality of memory components.

13. The system of claim 12, wherein the second command is a Per Dynamic Random Access Memory (PDA) command or a Per Buffer Addressability (PBA) command.

14. The system of claim 5, wherein the second command is a Per Dynamic Random Access Memory (PDA) command or a Per Buffer Addressability (PBA) command, and the memory component control mode is a PDA mode or a PBA mode.

15. The system of claim 5, wherein the plurality of memory components correspond to double date rate 4 (DDR4) synchronous dynamic random access memories (SDRAMs).

16. A non-transitory computer readable storage device storing computer-executable instructions, that when executed by at least one processor, causes the at least one processor to perform operations comprising:

receiving, at a memory controller, a plurality of memory settings to be applied to a plurality of memory components;

based on the received memory settings, transmitting a first command to the plurality of memory components, the first command causing each memory component of the plurality of memory components to be configured to a first memory setting;

based on the received memory settings, transmitting a second command to a subset of the plurality of memory components after transmitting the first command, the second command causing each memory component of the subset to be configured to a second memory setting; and

comparing the plurality of memory settings to determine a number of memory components of a second subset of the plurality of memory components, wherein each memory component of the second subset is associated with the first memory setting, and wherein the first command is transmitted in response to the number of memory components of the second subset satisfying a threshold;

wherein to transmit the second command, the memory controller is further configured to transmit the second command to the subset while a memory component control mode is activated.

17. The computer readable storage device of claim 16, wherein transmitting the second command comprises:

activating a memory component control mode; and

deactivating the memory component control mode after transmitting the second command.