Automation for monolithic 3D devices
First Claim
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1. A method of designing a 3D Integrated Circuit, the method comprising:
- performing partitioning to at least a first strata and a second strata;
thenperforming a first placement of said first strata using a 2D placer executed by a computer,wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and
performing a second placement of said second strata based on said first placement,wherein said partitioning comprises a partition between logic and memory,wherein said logic comprises at least one decoder representation for said memory,wherein said at least one decoder representation has a virtual size with width of contacts for through silicon vias,wherein said performing a first placement comprises using said decoder representation instead of an actual memory decoder, andwherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit.
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Abstract
A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a first strata and a second strata; then performing a first placement of the first strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of the second strata based on the first placement, where the partitioning includes a partition between logic and memory, and where the logic includes at least one decoder representation for the memory.
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18 Claims
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1. A method of designing a 3D Integrated Circuit, the method comprising:
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performing partitioning to at least a first strata and a second strata;
thenperforming a first placement of said first strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and performing a second placement of said second strata based on said first placement, wherein said partitioning comprises a partition between logic and memory, wherein said logic comprises at least one decoder representation for said memory, wherein said at least one decoder representation has a virtual size with width of contacts for through silicon vias, wherein said performing a first placement comprises using said decoder representation instead of an actual memory decoder, and wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit. - View Dependent Claims (2, 3, 4, 5)
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6. A method of designing a 3D Integrated Circuit, the method comprising:
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performing partitioning to at least a first strata and a second strata;
thenperforming a first placement of said first strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and performing a second placement of said second strata based on said first placement, wherein said partitioning comprises a partition between logic and memory, wherein said logic comprises at least one decoder for said memory wherein said memory comprises at least a first memory and a second memory, wherein said first memory comprises first memory decoders and said second memory comprises second memory decoders, wherein said 2D placer is set so said second memory decoders are not placed within a rectangle defined by the placement of said first memory decoders, and wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A method of designing a 3D Integrated Circuit, the method comprising:
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performing partitioning to at least a first strata and a second strata;
thenperforming a first placement of said first strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and performing a second placement of said second strata based on said first placement, wherein said partitioning comprises a partition between logic and memory, wherein said partition comprises a step of assigning at least one memory block to a logic strata for improved balancing of said logic strata area and a memory strata area, and wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification