Apparatuses and methods including two transistor-one capacitor memory and for accessing same

• US 10,127,972 B2
• Filed: 08/16/2017
• Issued: 11/13/2018
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kawamura, Christopher J., Derner, Scott J.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US15/679,042
• Publication Number:
  US 20180061477A1
• Time in Patent Office: 454 Days
• Field of Search: 365149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2211/4013 Memory devices with multiple cells per bit, e.g. twin-cells
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

Claims

1. An apparatus comprising a first memory array and a plurality of first sense amplifiers,

wherein the first memory array comprises:

a plurality of first pairs of word lines, each of the plurality of first pairs of word lines including first and second word lines, the first and second word lines being configured to be driven independently of each other;

a plurality of first pairs of digit lines, each of the plurality of first pairs of digit lines including first and second digit lines, the first and second digit lines being configured to be driven independently of each other; and

a plurality of first memory cells, each of the first memory cells being coupled to an associated one of the plurality of first pairs of word lines and an associated one of the plurality of first pairs of digit lines, each of the first memory cells comprising first and second transistors and a first capacitor between the first and second transistors, the first and second transistors and the first capacitor being coupled in series between the first and second digit lines of the associated one of the plurality of first pairs of digit lines; and

the first and second transistor having first and second gates, respectively, the first and second gates being coupled respectively to the first and second word lines of the associated one of the plurality of first pairs of word lines; and

wherein each of first sense amplifiers including first and second sense nodes, the first node being coupled to the first digit line of an associated one of the plurality of first pairs of digit lines, wherein the second digit lines of the plurality of first pairs of digit lines are coupled to each other.

2. The apparatus of claim 1, wherein the second sense node of each of the first sense amplifiers is supplied with a reference voltage to compare a voltage at the first sense node with the reference voltage.

3. The apparatus of claim 1, further comprising a semiconductor base and an insulating film over the semiconductor base, the first memory array being formed over the insulating film.

4. The apparatus of claim 3, wherein each of the first sense amplifiers is formed in the semiconductor base.

5. The apparatus of claim 3, wherein each of the first sense amplifier is formed between the memory array and the semiconductor base.

6. The apparatus of claim 1, further comprising a second memory array and a plurality of second sense amplifiers;

wherein the second memory array comprises;

a plurality of second pairs of word lines, each of the plurality of second pairs of word lines including third and fourth word lines, the third and fourth word lines being configured to be driven independently of each other;

a plurality of second pairs of digit lines, each of the plurality of second pairs of digit lines including third and fourth digit lines, the third and fourth digit lines being configured to be driven independently of each other; and

a plurality of second memory cells, each of the second memory cells being coupled to an associated one of the plurality of second pairs of word lines and an associated one of the plurality of second pairs of digit lines, each of the second memory cells comprising third and fourth transistors and a second capacitor between the third and fourth transistors, the third and fourth transistors and the second capacitor being coupled in series between the third and fourth digit lines of the associated one of the plurality of second pairs of digit lines, and the third and fourth transistor having third and fourth gates, respectively, the third and fourth gates being coupled respectively to the third and fourth word lines of the associated one of the plurality of second of digit lines;

wherein each of second sense amplifiers including third and fourth sense nodes, the third node being coupled to the third digit line of an associated one of the plurality of second pairs of digit lines; and

wherein the second digit line of each of the plurality of first pairs of digit lines is coupled to the fourth digit line of an associated one of the plurality of second pairs of digit lines.

7. The apparatus of claim 3, wherein the second sense node of each of the first sense amplifiers is supplied with a reference voltage to compare a voltage at the first sense node with the reference voltage, and wherein the fourth sense node of each of the second sense amplifiers is supplied with the reference voltage to compare a voltage at the third sense node with the reference voltage.

8. The apparatus of claim 1, wherein the first memory array comprises a conductive plate that serves as the second digit lines of the plurality of first pairs of digit lines.