Memory device and memory system performing request-based refresh, and operating method of the memory device

• US 10,127,974 B2
• Filed: 03/01/2018
• Issued: 11/13/2018
• Est. Priority Date: 11/06/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Hyun-Joong, Song, Ho-young, Chung, Hoi-ju, Jung, Ju-yun, Cha, Sang-uhn
• Primary Examiner(s): Dinh, Son
• Application Number:
  US15/909,220
• Publication Number:
  US 20180190340A1
• Time in Patent Office: 257 Days
• Field of Search: 365 51, 365 63, 365222
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2211/4068 Voltage or leakage in refresh operations
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.

Claims

1. A memory system comprising:

a memory controller configured to receive a request signal, and output a first refresh command in response to the request signal; and

a memory device comprising;

a weak row detector configured to count an activated number of a first row during a predefined time period, compare the activated number with a first threshold number, and determine at least one row adjacent to the first row as a disturbed row when the activated number is equal to or greater than the first threshold number;

a refresh timing determiner configured to determine a refresh state of the disturbed row;

a refresh signal generator configured to generate the request signal based on determining the refresh state of the disturbed row, and transmit the request signal to the memory controller; and

a refresh controller configured to perform a request-based refresh on the disturbed row in response to the first refresh command received from the memory controller.

2. The memory system of claim 1, wherein the memory controller is further configured to output a plurality of second refresh commands to the memory device for performing a normal refresh operation on each of a plurality of memory cell rows within a refresh period.

3. The memory system of claim 1, wherein the request signal is transmitted to the memory controller through a side channel which is separated from a command channel, an address channel and a data channel established between the memory controller and the memory device.

4. The memory system of claim 1, wherein the request signal is transmitted to the memory controller through a ready/busy signal and at least one of a command channel, an address channel and a data channel established between the memory controller and the memory device.

5. The memory system of claim 4, wherein the request signal is transmitted when the ready/busy signal is in a busy state.

6. The memory system of claim 1, wherein the refresh state of the disturbed row is determined by estimating a time interval between a first point of time on which the disturbed row is last refreshed and a second point of time on which the weak row detector determines the disturbed row.

7. The memory system of claim 6, wherein, the refresh signal generator is configured to generate the request signal when the time interval is equal to or greater than a predetermined threshold value, and not to generate the request signal when the time interval is smaller than the predetermined threshold value.

8. The memory system of claim 1, wherein the weak row detector is configured to determine two rows directly adjacent to the first row as two disturbed rows when the activated number is equal to or greater than the first threshold number, and the two disturbed rows are sequentially refreshed in response to the first refresh command.

9. The memory system of claim 1, wherein the request-based refresh is performed between normal refresh operations.

10. A memory device including a plurality of memory cell rows, the memory device comprising:

a weak row detector configured to count an activated number of a first row during a predefined time period, compare the activated number with a first threshold number, and determine at least one row adjacent to the first row as a disturbed row when the activated number is equal to or greater than the first threshold number;

a refresh timing determiner configured to determine a refresh state of the disturbed row;

a refresh signal generator configured to generate a request signal based on determining the refresh state of the disturbed row, and transmit the request signal to an external device; and

a refresh controller configured to perform a request-based refresh on the disturbed row in response to a first refresh command received from the external device.

11. The memory device of claim 10, further configured to receive a plurality of second refresh commands for performing a normal refresh operation on each of the plurality of memory cell rows within a refresh period.

12. The memory device of claim 10, wherein the request signal is transmitted to the external device through a side channel which is separated from a command channel, an address channel and a data channel.

13. The memory device of claim 10, wherein the request signal is transmitted to the external device through a ready/busy signal and at least one of a command channel, an address channel and a data channel.

14. The memory device of claim 13, wherein the request signal is transmitted when the ready/busy signal is in a busy state.

15. The memory device of claim 10, wherein the refresh state of the disturbed row is determined by estimating a time interval between a first point of time on which the disturbed row is last refreshed and a second point of time on which the weak row detector determines the disturbed row.

16. The memory device of claim 15, wherein, the refresh signal generator is configured to generate the request signal when the time interval is equal to or greater than a predetermined threshold value, and not to generate the request signal when the time interval is smaller than the predetermined threshold value.

17. The memory device of claim 10, wherein the weak row detector determines two rows directly adjacent to the first row as two disturbed rows when the activated number is equal to or greater than the first threshold number, and the two disturbed rows are sequentially refreshed in response to the first refresh command.

18. The memory device of claim 10, wherein the request-based refresh is performed between normal refresh operations.

19. The memory device of claim 10, wherein the memory device further includes an address information storage unit for storing a weak row address, the weak row address indicates a weak row which is identified to have low data retention characteristics during a test procedure.

20. The memory device of claim 19, wherein the refresh controller is further configured to perform a target refresh on the weak row address in addition to a normal refresh, thereby the weak row address is refreshed at least two times during a refresh period.