Semiconductor device having channel regions

• US 10,128,379 B2
• Filed: 07/12/2017
• Issued: 11/13/2018
• Est. Priority Date: 01/04/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Seung Min, Park, Woo Seok, Bae, Geum Jong, Bae, Dong Il, Yang, Jung Gil
• Primary Examiner(s): Stark, Jarrett
• Application Number:
  US15/647,903
• Publication Number:
  US 20180190829A1
• Time in Patent Office: 489 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.

Claims

1. A semiconductor device comprising:

a substrate;

protruding portions extending in parallel to each other on the substrate;

nanowires provided on the protruding portions and separated from each other;

gate electrodes provided on the substrate and surrounding the nanowires;

source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and

first voids provided between the source/drain regions and the protruding portions.

2. The semiconductor device of claim 1, further comprising inner spacers provided on the sides of the gate electrodes, and between the nanowires, and between a lowermost nanowire among the nanowires and the substrate.

3. The semiconductor device of claim 2, wherein, in a cross section taken in a first direction in which the protruding portions are extended, the first voids are sealed by the source/drain regions, the protruding portions, and lowermost inner spacers of the inner spacers.

4. The semiconductor device of claim 2, wherein one side surface of each of the inner spacers has a convex shape toward the gate electrodes.

5. The semiconductor device of claim 2, further comprising an insulating layer provided between the protruding portions and the first voids.

6. The semiconductor device of claim 5, wherein the insulating layer is in contact with a lowermost inner spacer of the inner spacers.

7. The semiconductor device of claim 1, wherein a lower surface of each of the source/drain regions is lower than a lowermost nanowire of the nanowires.

8. The semiconductor device of claim 1, further comprising:

an isolation insulating layer provided on the substrate and covering a portion of a side surface of each of the protruding portions; and

fin spacers provided on the isolation insulating layer and in contact with side surfaces of the protruding portions.

9. The semiconductor device of claim 8, wherein an upper end of each of the fin spacers is higher than an upper surface of a lowermost nanowire among the nanowires, and is lower than a lower surface of a neighboring nanowire adjacent to the lowermost nanowire.

10. The semiconductor device of claim 8, wherein an upper end of each of the fin spacers is higher than an upper surface of each of the protruding portions.

11. The semiconductor device of claim 8, wherein, in a cross section taken in a direction in which the gate electrodes are extended, each of the first voids is sealed by each of the source/drain regions, the fin spacers, and the protruding portions.

12. The semiconductor device of claim 8, wherein each of the source/drain regions includes a first portion provided between the fin spacers and having a first width, and a second portion provided on the first portion and having a second width that is wider than the first width of the second portion.

13. The semiconductor device of claim 1, further comprising an insulating layer provided between the protruding portions and the first voids.

14. A semiconductor device comprising:

a substrate;

protruding portions extending in parallel to each other on the substrate;

an isolation insulating layer provided on the substrate and covering a portion of side surfaces of the protruding portions;

fin spacers provided on the isolation insulating layer and in contact with the side surfaces of the protruding portions;

first channel regions provided on the protruding portions, the first channel regions being separated from each other and extended in a first direction;

second channel regions provided above the first channel regions and extended in the first direction;

gate electrodes extended in a second direction intersecting the first direction and surrounding the first channel regions and the second channel regions;

inner spacers provided on sides of the gate electrodes, and between the first channel regions and the protruding portions;

source/drain regions provided on the protruding portions and the sides of the gate electrodes, the source/drain regions being connected to the first channel regions and the second channel regions; and

first voids provided between the source/drain regions and the protruding portions.

15. The semiconductor device of claim 14, further comprising an insulating layer provided between the first voids and the substrate,

wherein the insulating layer is in contact with the inner spacers, and covers the protruding portions and the fin spacers.

16. The semiconductor device of claim 15, wherein, in a cross section taken in a direction in which the protruding portions are extended, the first voids are sealed by the source/drain regions, the insulating layer, and the inner spacers.

17. The semiconductor device of claim 14, further comprising an interlayer insulating layer covering the isolation insulating layer and the source/drain regions.

18. The semiconductor device of claim 17, further comprising an insulating layer provided between the first voids and the substrate,

wherein, in a cross section taken in a direction in which the gate electrodes are extended, the first voids are sealed by the source/drain regions, the insulating layer, the fin spacers, and the interlayer insulating layer.

19. The semiconductor device of claim 18, wherein the first voids are integrally provided on neighboring protruding portions of the protruding portions.

20. A semiconductor device comprising:

a substrate;

protruding portions extending in parallel to each other on the substrate;

source/drain regions provided on the protruding portions and extended in a direction perpendicular to an upper surface of the substrate;

nanowires providing a channel region extended in a first direction between the source/drain regions and separated from each other;

a gate electrode surrounding the nanowires and extended in a second direction intersecting the first direction;

a gate insulating film provided between the nanowires and the gate electrode; and

voids provided between the source/drain regions and the protruding portions,

wherein an upper boundary of the voids is lower than a lower surface of a lowermost nanowire among the nanowires.