Semiconductor substrate, semiconductor device, and manufacturing methods thereof

• US 10,128,403 B2
• Filed: 07/03/2017
• Issued: 11/13/2018
• Est. Priority Date: 06/10/2009
• Status: Active Grant

• Current Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Inventors: Sakai, Shiro
• Primary Examiner(s): Sandvik, Benjamin
• Application Number:
  US15/640,585
• Publication Number:
  US 20170338370A1
• Time in Patent Office: 498 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02642 Mask materials other than SiO2 or SiN
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 33/0066 with a substrate not being a III-V compound
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous

Abstract

A method of manufacturing a semiconductor substrate including forming a first layer on a substrate, patterning the first layer to form a plurality of patterns spaced apart from one another, forming a second layer on the patterns to cover each of the patterns, heat-treating the second layer to form cavities in the patterns between the second layer and the substrate, and growing the second layer covering the cavities.

Claims

1. A method of manufacturing a semiconductor substrate, the method comprising:

forming a first layer on a substrate;

patterning the first layer to form a plurality of patterns spaced apart from one another;

forming a second layer on the patterns to cover the entire upper surface of each of the patterns;

heat-treating the second layer to form cavities in the patterns between the second layer and the substrate; and

growing the second layer covering the cavities.

2. The method of claim 1, wherein heat-treating the second layer comprises heat-treating the second layer at a temperature greater than 900 °

C.

3. The method of claim 1, wherein the second layer further comprises at least one of gallium and nitrogen.

4. The method of claim 3, wherein the second layer further comprises aluminum.

5. The method of claim 1, wherein the substrate comprises at least one of a sapphire substrate and a silicon-based substrate.

6. The method of claim 1, wherein the first layer comprises at least one of titanium and tantalum.

7. The method of claim 6, wherein the first layer further comprises oxygen.

8. A method of manufacturing a semiconductor substrate, the method comprising:

forming a first layer on a substrate;

patterning the first layer to form a plurality of patterns spaced apart from one another;

forming a second layer on the patterns to cover each of the patterns;

heat-treating the second layer to form cavities in the patterns between the second layer and the substrate; and

growing the second layer covering the cavities,

wherein a cross-sectional view of the patterns has substantially a semi-spherical shape.

9. The method of claim 8, wherein the substrate comprises at least one of a sapphire substrate and a silicon-based substrate.

10. The method of claim 8, wherein the first layer comprises at least one of titanium and tantalum.

11. A method of manufacturing a semiconductor substrate, the method comprising:

forming a first layer on a substrate;

patterning the first layer to form a plurality of patterns spaced apart from one another;

forming a second layer on the patterns to cover each of the patterns;

heat-treating the second layer to form cavities in the patterns between the second layer and the substrate; and

growing the second layer covering the cavities,

wherein the cavities are directly formed on the substrate.

12. The method of claim 11, wherein the substrate comprises at least one of a sapphire substrate and a silicon-based substrate.

13. The method of claim 11, wherein the first layer comprises at least one of titanium and tantalum.

14. A method of manufacturing a semiconductor substrate, the method comprising:

forming a first layer on a substrate;

patterning the first layer to form a plurality of patterns spaced apart from one another;

forming a second layer on the patterns to cover each of the patterns;

heat-treating the second layer to form cavities in the patterns between the second layer and the substrate; and

growing the second layer covering the cavities,

wherein at least portions of the patterns evaporate through a first portion of the second layer.

15. The method of claim 14, wherein the substrate comprises at least one of a sapphire substrate and a silicon-based substrate.

16. The method of claim 14, wherein the first layer comprises at least one of titanium and tantalum.

17. A method of manufacturing a semiconductor substrate, the method comprising:

forming a first layer on a substrate;

patterning the first layer to form a plurality of patterns spaced apart from one another;

forming a second layer on the patterns to cover each of the patterns;

heat-treating the second layer to form cavities in the patterns between the second layer and the substrate, and to crystalize the second layer at a first temperature; and

growing the second layer covering the cavities.

18. The method of claim 17, wherein the substrate comprises at least one of a sapphire substrate and a silicon-based substrate.

19. The method of claim 17, wherein the first layer comprises at least one of titanium and tantalum.