Optoelectronic component and method for the production thereof

• US 10,128,405 B2
• Filed: 06/03/2009
• Issued: 11/13/2018
• Est. Priority Date: 06/06/2008
• Status: Active Grant

• Current Assignee: OSRAM OLED GMBH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: Kaiser, Stephan, Ploessl, Andreas
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): Culbert, Christopher
• Application Number:
  US12/996,622
• Publication Number:
  US 20110210357A1
• Time in Patent Office: 3,450 Days
• Field of Search: 257 98
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/405 Reflective materials

Abstract

A method of producing an optoelectronic component, comprising the method steps: A) providing a growth substrate (1); B) growing at least one semiconductor layer (2) epitaxially, to produce an operationally active zone; C) applying a metallic mirror layer (3) to the semiconductor layer (2); D) applying at least one contact layer (8) for electronic contacting of the component; E) detaching the growth substrate (1) from the semiconductor layer (2), so exposing a surface of the semiconductor layer (2); and F) structuring the semiconductor layer (2) by means of an etching method from the side of the surface which was exposed in method step E).

Claims

1. A method of producing an optoelectronic component, comprising the steps of:

A) providing a growth substrate;

B1) growing a semiconductor layer sequence epitaxially comprising a plurality of semiconductor layers and an operationally active zone;

B2) applying a low refractive index dielectric to the semiconductor layer sequence;

B3) structuring the low refractive index dielectric so that the low refractive index dielectric is removed in sub-regions;

C1) applying a metallic mirror layer to the semiconductor layer sequence and to the low refractive index dielectric so that a side of the metallic mirror layer facing the semiconductor layer sequence is structured and the metallic mirror layer penetrates the low refractive index dielectric in the sub-regions where the low refractive index dielectric has been removed so that the metallic mirror layer extends as far as the semiconductor layer sequence;

C2) removing a sub-region of the metallic mirror layer and applying a diffusion barrier layer to the metallic mirror layer so that the diffusion barrier layer extends as far as the low refractive index dielectric;

D) applying at least one contact layer for electronic contacting of the component;

E) detaching the growth substrate from the semiconductor layer sequence, for exposing a surface of the at least one semiconductor layer; and

F) structuring the semiconductor layer sequence via an etching method from the side of the surface which was exposed in method step E), wherein trenches are produced, by means of which the semiconductor layer sequence is subdivided into a plurality of sub-regions, wherein the trenches penetrate the semiconductor layer sequence in a direction towards the metallic mirror layer completely.

2. The method according to claim 1, wherein the cross-sections of the trenches produced in method step F) taper from the surface exposed in method step E) towards the metallic mirror layer.

3. The method according to claim 1, further comprising the following method steps between method steps C2) and D):

G) applying a passivation layer to the diffusion barrier layer.

4. The method according to claim 1, wherein the layer sequence produced in method steps A) to F) is applied to a carrier, which is produced by a method comprising the steps of:

I1) providing a carrier wafer;

I2) applying a barrier layer to the carrier wafer; and

I3) applying a bonding layer to the barrier layer.

5. The method according to claim 1, further comprising, after method step F), step J1) roughening the structured semiconductor layer sequence.

6. The method according to claim 5, further comprising, after method step J1), step J2) coating the roughened semiconductor layer sequence with a top coat which is transmissive for visible radiation, UV radiation, IR radiation, or any combination of these radiations.

7. The method according to claim 6, further comprising, after method step J2), step J3) structuring the top coat.

8. The method according to claim 7, further comprising, after method step J3), step J4) applying an electrical contact to a sub-region of the semiconductor layer sequence re-exposed by the structuring of the top coat.

13. The method according to claim 1, wherein SiO₂ is used for the low refractive index dielectric.

14. The method according to claim 1, wherein the low refractive index dielectric has a refractive index of 1.553 or less.

9. A method of producing an optoelectronic component, comprising the steps of:

A) providing a growth substrate;

B1) growing a semiconductor layer sequence epitaxially, comprising a plurality of semiconductor layers and an operationally active zone;

B2) applying a low refractive index dielectric to the semiconductor layer sequence;

B3) structuring the low refractive index dielectric, wherein the low refractive index dielectric is removed in sub-regions;

C1) applying a metallic mirror layer to the semiconductor layer sequence and to the low refractive index dielectric so that the side of the metallic mirror layer facing the semiconductor layer sequence is structured and the metallic mirror layer penetrates the low refractive index dielectric in the sub-regions where the low refractive index dielectric has been removed such that the metallic mirror layer extends as far as the semiconductor layer sequence;

C2) removing a sub-region of the metallic mirror layer and applying a diffusion barrier layer to the metallic mirror layer such that the diffusion barrier layer extends as far as the low refractive index dielectric;

D) applying at least one contact layer for electrical contacting of the component; and

E) detaching the growth substrate from the semiconductor layer sequence for exposing a surface of the semiconductor layer sequence, wherein at least one mesa trench is formed in the semiconductor layer sequence from the side of the exposed surface of the semiconductor layer sequence only after the step of detaching the growth substrate from the semiconductor layer sequence, wherein the trench penetrates the semiconductor layer sequence in a direction towards the metallic mirror layer completely.

10. The method according to claim 9, wherein the at least one mesa trench is formed by an wet etching method such that the at least one mesa trench tapers when viewed from the exposed surface of the semiconductor layer sequence towards the mirror layer.

11. The method according to claim 9, wherein a plurality of trenches are formed in the semiconductor layer sequence only after the step of detaching the growth substrate from the semiconductor layer sequence in such a way that the trenches penetrate the semiconductor layer sequence so that the semiconductor layer sequence is subdivided into a plurality of sub-regions by means of the plurality of the trenches.

12. The method according to claim 11, wherein the exposed surface of the semiconductor layer sequence is roughened and then provided with a top coat, said top coat also extending into the trenches and being formed of bisbenzocyclobutene.