Fluid pressure activated electrical contact devices and methods
DCFirst Claim
1. An microelectronic structure having CTE (co-efficient of thermal expansion) compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween and a spring structure spanning the gap and connecting the adjacent tiles, the spring structure configured to permit movement of the adjacent tiles relative to one another to provide compensation for thermal expansion or contraction of the tiles;
- a respective opening extending through each substrate tile from the upper surface to an opposing lower surface;
an electrically conductive post extending through each opening from the upper surface to the lower surface; and
a device layer attached above the upper surfaces of the common plane.
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Abstract
A contactor device includes: a first body substrate; a second body substrate; a flexible membrane connected to the first body substrate and second body substrate, wherein the second substrate body is movable relative to the first substrate body by flexure of the flexible membrane; an electrical contact member carried by the second substrate body; a microfluidic-channeled substrate coupled to the first body substrate, the microfluidic-channeled substrate having a chamber and a microfluidic channel in fluid communication with the chamber; and a 3-dimensional flexible membrane enclosing the chamber, wherein the 3-dimensional flexible membrane flexes toward the second body substrate when a fluid pressure is applied to the chamber through the microfluidic channel whereby a force or a movement is transferred to the second body substrate by the 3-dimensional flexible membrane.
52 Citations
26 Claims
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1. An microelectronic structure having CTE (co-efficient of thermal expansion) compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween and a spring structure spanning the gap and connecting the adjacent tiles, the spring structure configured to permit movement of the adjacent tiles relative to one another to provide compensation for thermal expansion or contraction of the tiles;
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a respective opening extending through each substrate tile from the upper surface to an opposing lower surface; an electrically conductive post extending through each opening from the upper surface to the lower surface; and a device layer attached above the upper surfaces of the common plane. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of forming a three-dimensional microstructure by a sequential build process, comprising:
- disposing a plurality of layers over a substrate, wherein the layers comprise one or more layers of a conductive material and one or more layers of a sacrificial material, thereby forming a structure above the substrate, comprising;
a plurality of conductive tiles formed of one or more layers of the conductive material, each tile having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween and a spring structure spanning the gap and connecting the adjacent tiles, the spring structure configured to permit movement of the adjacent tiles relative to one another to provide compensation for thermal expansion or contraction of the tiles;a respective opening extending through each substrate tile from the upper surface to an opposing lower surface; an electrically conductive post extending through each opening from the upper surface to the lower surface; and a device layer attached above the upper surfaces of the common plane. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
- disposing a plurality of layers over a substrate, wherein the layers comprise one or more layers of a conductive material and one or more layers of a sacrificial material, thereby forming a structure above the substrate, comprising;
Specification