Wireless communication link using near field coupling

• US 10,128,916 B2
• Filed: 03/14/2016
• Issued: 11/13/2018
• Est. Priority Date: 12/11/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Abdulla, Mostafa Naguib
• Primary Examiner(s): Talukder, Md
• Application Number:
  US15/069,813
• Publication Number:
  US 20160197653A1
• Time in Patent Office: 974 Days
• Field of Search: 455 411, 455 412, 455 413
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1434 Memory
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H01Q 7/00 Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
• CPC Class Codes: H01Q 7/005 with variable reactance for tuning the antenna
• CPC Class Codes: H04B 5/00 : Near-field transmission systems, e.g. inductive or capacitive transmission systems
• CPC Class Codes: H04B 5/26 : using coils
• CPC Class Codes: H04B 5/48 : Transceivers
• CPC Class Codes: H04B 5/72 : for local intradevice communication

Abstract

A memory device may include an array of closely spaced memory integrated circuits that communicate wirelessly over at least two frequencies using near field coupling.

Claims

1. An apparatus comprising:

a substrate having an upper surface, a lower surface opposite the upper surface, and a plurality of side surfaces perpendicular to and extending between the upper surface and the lower surface;

an upper loop antenna on the upper surface;

a lower loop antenna on the lower surface; and

a plurality of loop antennas, each loop antenna of the plurality of loop antennas parallel to a respective side surface of the plurality of side surfaces and transversely oriented to the upper loop antenna and the lower loop antenna, the loop antenna comprising;

a first portion of the loop antenna on the upper surface;

a second portion of the loop antenna on the lower surface; and

a via coupling the first portion of the loop antenna to the second portion of the loop antenna.

2. The apparatus of claim 1, wherein each loop antenna of the plurality of loop antennas comprises:

a third portion of the loop antenna on the upper surface; and

a second via coupling the third portion of the loop antenna to the second portion of the loop antenna.

3. The apparatus of claim 2, wherein the first and third portions comprise conductive strips plated or printed on the upper surface.

4. The apparatus of claim 2, wherein the second portion comprises an internal conductive layer plated or printed on the lower surface.

5. The apparatus of claim 1, further comprising an integrated circuit chip located on the upper surface and configured to control the upper loop antenna, the lower loop antenna, and the plurality of loop antennas.

6. The apparatus of claim 5, wherein the integrated circuit chip is at least partially surrounded by the upper loop antenna.

7. An apparatus comprising:

an array of memory integrated circuits, wherein each memory integrated circuit comprises;

a substrate having top face, a bottom face opposite the top face, and a plurality of side faces perpendicular to and extending between the top face and the bottom face;

a first loop antenna within the substrate and adjacent to the top face;

a second loop antenna within the substrate and adjacent to the bottom surface; and

a plurality of side loop antennas, each side loop antenna of the plurality of side loop antennas having a first portion within the top face of the substrate and a second portion within the bottom face of the substrate, the first portion electrically coupled to the second portion, wherein each of the plurality of side loop antennas is adjacent to and parallel to a side face of the plurality of side faces and is transversely oriented to the first loop antenna and the second loop antenna.

8. The apparatus of claim 7, wherein a first memory integrated circuit of the array is communicatively coupled to a second memory integrated circuit of the array by near field communication.

9. The apparatus of claim 8, wherein a single loop antenna of the first memory integrated circuit is communicatively coupled to a single loop antenna of the second memory integrated circuit.

10. The apparatus of claim 9, wherein the single loop antenna of the first memory integrated circuit is parallel to the single loop antenna of the second memory integrated circuit.

11. The apparatus of claim 8, wherein the first memory integrated circuit is physically coupled to the second memory integrated circuit.

12. The apparatus of claim 7, wherein the first loop antenna and the second loop antenna are each perpendicular to each of the side loop antennas.

13. The apparatus of claim 7, wherein each memory integrated circuit in the array of memory integrated circuits comprises an integrated circuit chip located on the top face and surrounded by the first loop antenna.

14. An apparatus comprising:

a substrate having a plurality of orthogonal faces, including a top face and a bottom face positioned opposite the top face;

an upper loop antenna proximate the top face;

a lower loop antenna proximate the bottom face;

a plurality of loop antennas, wherein each loop antenna of the plurality of loop antennas is located adjacent to and parallel to one of the plurality of orthogonal faces, at least one of the plurality of loop antennas comprising a first portion proximate the top face and a second portion proximate the bottom face, the first portion electrically coupled to the second portion, wherein each loop antenna of the plurality of loop antennas is transversely oriented relative the upper loop antenna and the lower loop antenna; and

an integrated circuit chip configured to control transmission of information from the plurality of loop antennas.

15. The apparatus of claim 14, wherein the integrated circuit chip is located on one face of the plurality of orthogonal faces.

16. The apparatus of claim 14, wherein the integrated circuit chip is located within a loop antenna of the plurality of loop antennas.

17. The apparatus of claim 14, wherein the integrated circuit chip is coupled to each loop antenna of the plurality of loop antennas by a wire bond.

18. The apparatus of claim 14, wherein each face in the plurality of orthogonal faces is perpendicular to each adjacent face of the plurality of orthogonal faces.

19. The apparatus of claim 14, wherein each loop antenna of the plurality of loop antennas is configured to communicate with a corresponding loop antenna in a neighboring apparatus by near field coupling.