Coupled inverter with auto-calibration

• US 10,128,965 B1
• Filed: 09/01/2017
• Issued: 11/13/2018
• Est. Priority Date: 09/01/2017
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Wilson, Thomas E., Chae, Moo Sung
• Primary Examiner(s): Guarino, Rahel
• Application Number:
  US15/694,418
• Time in Patent Office: 438 Days
• CPC Class Codes: H03K 19/0021 Modifications of threshold for electronic switching or gating H03K17/30
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 5/082 with an adaptive threshold
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 17/21 for calibration; for correcting measurements

Abstract

A device including an input configured to receive an input signal in an operational mode and to receive a reference voltage in a calibration mode is provided. The device includes a capacitor to store a reference charge based on the reference voltage and an input inverter to capture a transition of the input signal. The input inverter is coupled in series with the capacitor so that the transition of the input signal occurs when a voltage of the input signal crosses the reference voltage. The device includes an output inverter coupled in series with the input inverter to provide an output signal having a parity of the input signal. A system including the above device, and a method for calibrating the above device, are also provided.

Claims

1. A device, comprising:

an input configured to receive an input signal in an operational mode and to receive a reference voltage in a calibration mode;

a capacitor configured to store a reference charge based on the reference voltage;

an input inverter configured to capture a transition of the input signal, the input inverter coupled in series with the capacitor so that the transition of the input signal occurs when a voltage of the input signal crosses the reference voltage; and

an output inverter, coupled in series with the input inverter, and configured to provide an output signal having a parity of the input signal.

2. The device of claim 1, further comprising an inverter switch configured to electrically couple an output node in the input inverter to an input node in the input inverter when the device is in the calibration mode, and to electrically decouple the output node and the input node when the device is in the operational mode.

3. The device of claim 1, further comprising a mode switch configured to electrically couple the input with the input signal in the operational mode and with the reference voltage in the calibration mode.

4. The device of claim 1, further comprising a filter to restore a high frequency component of the input signal.

5. The device of claim 1, wherein the reference voltage is constant, relative to a varying environmental condition, the varying environmental condition comprising one of a power, a voltage, and a temperature of the device.

6. The device of claim 1, wherein the input is configured to alternate between the operational mode and the calibration mode with a duty cycle that emphasizes the operational mode over the calibration mode.

7. The device of claim 1, wherein the input signal is a datum provided by a memory circuit when the device is located in a processor circuit coupled to the memory circuit, or by the processor circuit when the device is located in the memory circuit.

8. The device of claim 1, wherein the input signal is a digital signal configured in a non-return to zero protocol.

9. The device of claim 1, wherein a threshold voltage for the input inverter is maintained at the reference voltage when a common mode voltage of the input signal varies within a range comparable to the voltage of the input signal.

10. A system, comprising:

a first receiver channel comprising;

a first input configured to receive an input signal in a first operational mode and to receive a reference voltage in a first calibration mode;

an input inverter configured to capture a transition of the input signal when a voltage of the input signal crosses the reference voltage;

a second receiver channel configured to;

receive the input signal in a second operational mode, and

receive the reference voltage in a second calibration mode; and

a multiplexer configured to provide an output signal based on the input signal in a continuous overlap of the first operational mode and the second operational mode.

11. The system of claim 10, wherein the first receiver channel comprises an output inverter coupled in series with the input inverter to provide the output signal with a parity of the input signal.

12. The system of claim 10, wherein the first receiver channel comprises a capacitor to store a reference charge when the first channel is in the first calibration mode, and wherein the input inverter is coupled in series with the capacitor.

13. The system of claim 10, wherein the first receiver channel further comprises an inverter switch configured to electrically couple an output node in the input inverter to an input node in the input inverter when the system is in the first calibration mode, and to electrically decouple the output node and the input node when the system is in the first operational mode.

14. The system of claim 10, wherein the first receiver channel further comprises a mode switch configured to electrically couple the first input with the input signal in the first operational mode and with the reference voltage in the first calibration mode.

15. The system of claim 10, wherein the first receiver channel further comprises a filter to restore a high frequency component of the input signal.

16. The system of claim 10, wherein the reference voltage is constant relative to a varying environmental condition, the varying environmental condition comprising one of a power, a voltage, and a temperature of the system.

17. A method, comprising:

coupling an output of an inverting gate to an input of the inverting gate in a calibration mode of a receiver;

charging a capacitor disposed between a reference voltage and the input of the inverting gate when the input and the output of the inverting gate reach an equilibrium in the calibration mode;

coupling an input of the inverting gate to an input signal through the capacitor; and

interleaving an operational mode of the receiver with the calibration mode in a duty cycle.

18. The method of claim 17, wherein interleaving an operational mode of the receiver with the calibration mode comprises apportioning a smaller fraction of the duty cycle to the calibration mode relative to the operational mode.

19. The method of claim 17, further comprising, with the receiver, receiving an input signal comprising a datum from a processor, and providing a buffered output signal comprising the datum to a memory.

20. The method of claim 17, wherein the receiver comprises a first channel and a second channel, and a multiplexer coupled to the first channel, the second channel, and an output, the method further comprising providing, with the multiplexer and through the output, a buffered output signal alternatively from the first channel and the second channel to form a continuous output signal.