System and method for reducing false preamble detection in a communication receiver
First Claim
1. A packet detection circuit comprising:
- packet preamble detection circuit to indicate detection of a packet preamble based upon a succession of detected edge signals, each separated from an adjacent edge signal by at least a prescribed time interval, matching a prescribed preamble pattern; and
clearing circuitry to produce a signal to indicate false preamble detection in response to failure to receive packet information following an indication of an arrival of a packet preamble.
3 Assignments
0 Petitions
Accused Products
Abstract
An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
31 Citations
22 Claims
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1. A packet detection circuit comprising:
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packet preamble detection circuit to indicate detection of a packet preamble based upon a succession of detected edge signals, each separated from an adjacent edge signal by at least a prescribed time interval, matching a prescribed preamble pattern; and clearing circuitry to produce a signal to indicate false preamble detection in response to failure to receive packet information following an indication of an arrival of a packet preamble. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A packet detection circuit comprising:
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a counter circuit configured to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed count; a pattern matching circuit, coupled to the counter circuit, configured to match a sequence of detected edge signals, separated from each other by at least a prescribed time interval, with the prescribed pattern; and a logic processing circuit to indicate false preamble detection in response to failure to receive the packet information following the pattern matching circuit detecting a packet preamble.
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12. A packet detection method comprising:
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providing a signal to indicate detection of a packet preamble based upon a succession of detected edge signals, each separated from an adjacent edge signal by at least a prescribed time interval, matching a prescribed preamble pattern; and producing a signal to indicate false preamble detection in response to failure to receive packet information following an indication of an arrival of a packet preamble. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A packet detection method comprising:
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cyclically counting clock counts between successive detected edge signals; comparing the count reached between two of the successive detected edge signals with a threshold value matching a prescribed count; producing clock signal pulses in response to a provided indication indicating that the two of the successive detected edge signals a separated from each other by at least the prescribed count; phase matching to align the produced clock signal pulses with one of the successive detected edge signals; and producing a signal to indicate false preamble detection in response to failure to receive packet information following an indication of an arrival of a packet preamble.
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Specification