Methods for transmitting audio and video signals and transmission system thereof

• US 10,129,498 B2
• Filed: 12/16/2016
• Issued: 11/13/2018
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: Nanjing Silergy Semiconductor (Hong Kong) Technology Ltd.
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Shi, Weifeng, Xu, Jiangping
• Primary Examiner(s): Teitelbaum, Michael E
• Application Number:
  US15/381,666
• Publication Number:
  US 20170195608A1
• Time in Patent Office: 697 Days
• Field of Search: 348723, 348714, 348705, 348500, 348512, 348515, 348553, 348489, 348482, 348479, 348477, 348476, 348473, 348469, 348467, 348465, 348464, 348462, 348461, 348460, 348459, 348443, 348441, 348423, 3484231, 3484254, 3484261, 3484271, 370366, 37039564, 370463, 370464, 370465, 370466, 370467, 370468, 370470, 370472, 370473, 370476, 370479, 370503, 370522, 370535, 370536, 370537, 370541, 370542, 725 51, 725 54, 725 95, 725105, 725118, 725151, 725136
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 2380/10 Automotive applications
• CPC Class Codes: G09G 5/00 Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators image data processing or generation, in general G06T
• CPC Class Codes: H04N 5/38 Transmitter circuitry for the transmission of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 5/44 Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 5/60 for the sound signals
• CPC Class Codes: H04N 7/04 Systems for the transmission of one television signal, i.e. both picture and sound, by a single carrier H04N7/084, H04N7/087 take precedence
• CPC Class Codes: H04N 7/0887 for the transmission of programme or channel identifying signals

Abstract

Transmitting audio and video signals, can include: detecting if the state of a video control signal has changed, where a video signal includes the video control signal and a video data signal; generating, if the state of the video control signal has not changed, a first serial data packet based on the video signal and an audio signal; generating, if the state of the video control signal has changed, a second serial data packet based on the video signal and the audio signal; transmitting over a serial link, an encoded data frame formed by encoding the first and second serial data packets in a predetermined encoding manner; decoding and de-serializing the encoded data frame to restore the video signal and the audio signal; and outputting the video signal to a video display circuit, and outputting the audio signal to an audio processor respectively.

Claims

1. A method for transmitting audio and video signals, the method comprising:

a) detecting, by a detection circuit, if the state of a video control signal has changed, wherein a video signal comprises said video control signal and a video data signal;

b) generating, by a transmitting circuit if said state of said video control signal has not changed, a first serial data packet based on said video signal and an audio signal, wherein said audio signal comprises an audio data signal and an audio sampling rate signal that occupy one bit in said first serial data packet to form an audio information segment of said first serial data packet, and wherein a video information segment of said first serial data packet comprises said video data signal;

c) generating, by said transmitting circuit if said state of said video control signal has changed, a second serial data packet based on said video signal and said audio signal, wherein each of said audio data signal and said audio sampling rate signal occupies one bit in said second serial data packet to form said audio information segment of said second serial data packet, wherein said video information segment of said second serial data packet comprises said video control signal, and a plurality of special character bits, and wherein said video control signal comprises a horizontal synchronizing signal, a vertical synchronizing signal, and a data enable signal;

d) transmitting, to a receiving circuit over a serial link, an encoded data frame formed by encoding said first and second serial data packets in a predetermined encoding manner;

e) decoding and de-serializing, by said receiving circuit, said encoded data frame to restore said video signal and said audio signal; and

f) outputting said video signal to a video display circuit, and outputting said audio signal to an audio processor respectively, wherein said receiving circuit detects whether the currently received data packet is said first serial data packet or said second serial data packet based on said plurality of special character bits.

2. The method of claim 1, wherein said transmitting circuit further receives a forward control channel signal when forming said first and second serial data packets, such that each of said first and second serial data packets includes one forward control channel signal bit, and said forward control channel signal determines a number of channels and a word length of said audio data signal.

3. The method of claim 2, wherein a parity bit is arranged in both of said first and second serial data packets.

4. The method of claim 2, wherein said transmitting circuit further receives at least one auxiliary control signal such that both of said first and second serial data packets comprises at least one auxiliary control signal bit.

5. The method of claim 4, wherein the bits occupied by said audio sampling rate signal serve as an audio frame start bit.

6. The method of claim 5, wherein when said number of channels of said audio data is 2, said bits occupied by said audio sampling rate signal further serves as a channel selection bit.

7. The method of claim 2, wherein said receiving circuit restores said audio clock signal of said audio signal based on said bit occupied by said audio sampling rate signal and said forward control channel signal bit.

8. The method of claim 2, wherein the information of said special character bits comprises bit combinations not obtained by encoding said first serial data packet or said second serial data packet in said predetermined encoding manner.

9. The method of claim 2, wherein said predetermined encoding manner is an 8B/10B encoding manner, and said predetermined decoding manner is an 8B/10B decoding manner.

10. The method of claim 9, wherein:

a) said first and second serial data packets are both 32-bit data packets;

b) said first serial data packet comprises twenty-four video data signal bits, four auxiliary signal bits, one audio sampling rate signal bit, one audio data signal bit, one forward control channel bit and one parity bit; and

c) said second serial data packet comprises eight special character bits, thirteen idle bits, three video control signal bits, four auxiliary signal bits, one audio sampling signal bit, one audio data signal bit, one forward control channel bit and one parity bit, said three video control signal bits allocated to said horizontal synchronizing signal, said vertical synchronizing signal, and said data enable signal.

11. The method of claim 2, wherein said audio signal is synchronous with said video signal under the control of said video signal.

12. A system for transmitting audio and video signals, the system comprising:

a) a transmitting circuit configured to detect if the state of a video control signal has changed, wherein a video signal comprises said video control signal and a video data signal;

b) said transmitting circuit being configured to generate, if said state of said video control signal has not changed, a first serial data packet based on said video signal and an audio signal, wherein said audio signal comprises an audio data signal and an audio sampling rate signal that occupy one bit in said first serial data packet to form an audio information segment of said first serial data packet, and wherein a video information segment of said first serial data packet comprises said video data signal;

c) said transmitting circuit being configured to generate, if said state of said video control signal has changed, a second serial data packet based on said video signal and said audio signal, wherein each of said audio data signal and said audio sampling rate signal occupies one bit in said second serial data packet to form said audio information segment of said second serial data packet, wherein said video information segment of said second serial data packet comprises said video control signal, and a plurality of special character bits, and wherein said video control signal comprises a horizontal synchronizing signal, a vertical synchronizing signal, and a data enable signal;

d) a receiving circuit configured to receive over a serial link, an encoded data frame formed by encoding said first and second serial data packets in a predetermined encoding manner;

e) said receiving circuit being configured to decode and de-serialize said encoded data frame to restore said video signal and said audio signal; and

f) said receiving circuit being configured to output said video signal to a video display circuit, and to output said audio signal to an audio processor respectively, wherein said receiving circuit detects whether the currently received data packet is said first serial data packet or said second serial data packet based on said plurality of special character bits.

13. The system of claim 12, wherein said transmitting circuit is configured to receive a forward control channel signal when forming said first and second serial data packets, such that each of said first and second serial data packets comprises one forward control channel signal bit, and said forward control channel signal determines a number of channels and a word length of said audio data signal.

14. The system of claim 13, wherein said transmitting circuit comprises:

a) a detection circuit configured to receive said video control signal to detect if said video control signal has changed;

b) an audio serialization circuit configured to receive a parallelized audio signal outputted by an audio signal source, and to serialize said audio signal to form a serialized audio signal;

c) a video/audio serial circuit configured, when said detection circuit detects that the state of said video control signal has not changed, to control said serialized audio signal to be synchronous with said video signal based on a clock signal of said video signal, and to serialize said serialized audio signal, said parallelized video control signal, and said forward control channel signal, to generate said first serial data packet;

d) said video/audio serial circuit being configured, when said detection circuit detects that the state of said video control signal has changed, to control said serialized audio signal to be synchronous with said video signal based on said clock signal of said video signal, and to serialize said serialized audio signal, said parallelized video control signal, a plurality of special characters and said forward control channel signal, to generate said second serial data packet; and

e) an encoding circuit configured to encode said first and second serial data packets to form said encoded data frame, wherein said plurality of special characters comprises bit combinations not obtained by encoding said first serial data packet or said second serial data packet in said predetermined encoding manner.

15. The system of claim 13, wherein said receiving circuit comprises:

a) a decoding circuit configured to decode said encoded data frame to recover said first and second serial data packets;

b) a video/audio de-serialization circuit configured to de-serialize said first and second serial data packets to recover said parallelized video signal, said audio signal, and to transmit said recovered video signal to said video display circuit;

c) an audio de-serialization circuit configured to recover said serial audio data signal to said parallel audio data signal, and to transmit said recovered audio data signal to said audio processor; and

d) a clock recovery circuit configured to receive said audio sampling rate signal and recovers said clock signal of said audio signal based on audio information obtained according to said audio sampling rate signal and said forward control channel signal, and to output said clock signal of said audio signal to said audio processor.