Multilevel memory bus system
First Claim
1. A multilevel memory bus system for a solid-state storage device that includes a plurality of semiconductor memory devices, a host interface, at least one flash-specific-DMA controller, and a local processing system that includes a local memory, the multilevel memory bus system comprising:
- an intermediate bus disposed to couple to said at least one flash-specific DMA controller;
a first flash memory bus disposed to couple to at least one semiconductor memory device from the plurality of semiconductor memory devices, said at least one semiconductor memory device including a first semiconductor memory device;
a first flash buffer circuit coupled to said intermediate bus and to said first flash memory bus;
and wherein said intermediate bus is disposed to transfer data at a first data path transfer rate, said first flash memory bus is disposed to transfer data at a second data path transfer rate;
wherein said intermediate bus comprises a first data path having a first bus width;
wherein said intermediate bus comprises an interface data throughput that is defined by said first bus width, a first clock frequency of said intermediate bus, a second clock frequency of said first flash memory bus, an intermediate bus frequency factor which is a quotient of said first clock frequency and said second clock frequency, a selected data sampling rate, and a first strobe frequency of a first strobe signal wherein said selected data sampling rate permits a sampling of data on one edge of the first strobe signal per each strobe signal clock period or on two edges of the first strobe signal per each strobe signal clock period;
wherein said interface data throughput of said intermediate bus is defined by a multiplication of said first bus width, said intermediate bus frequency factor, said second clock frequency, and said selected data sampling rate.
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Abstract
The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.
343 Citations
36 Claims
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1. A multilevel memory bus system for a solid-state storage device that includes a plurality of semiconductor memory devices, a host interface, at least one flash-specific-DMA controller, and a local processing system that includes a local memory, the multilevel memory bus system comprising:
- an intermediate bus disposed to couple to said at least one flash-specific DMA controller;
a first flash memory bus disposed to couple to at least one semiconductor memory device from the plurality of semiconductor memory devices, said at least one semiconductor memory device including a first semiconductor memory device; a first flash buffer circuit coupled to said intermediate bus and to said first flash memory bus; and wherein said intermediate bus is disposed to transfer data at a first data path transfer rate, said first flash memory bus is disposed to transfer data at a second data path transfer rate; wherein said intermediate bus comprises a first data path having a first bus width; wherein said intermediate bus comprises an interface data throughput that is defined by said first bus width, a first clock frequency of said intermediate bus, a second clock frequency of said first flash memory bus, an intermediate bus frequency factor which is a quotient of said first clock frequency and said second clock frequency, a selected data sampling rate, and a first strobe frequency of a first strobe signal wherein said selected data sampling rate permits a sampling of data on one edge of the first strobe signal per each strobe signal clock period or on two edges of the first strobe signal per each strobe signal clock period; wherein said interface data throughput of said intermediate bus is defined by a multiplication of said first bus width, said intermediate bus frequency factor, said second clock frequency, and said selected data sampling rate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
- an intermediate bus disposed to couple to said at least one flash-specific DMA controller;
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21. A storage device, comprising:
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a local processing system that includes a local memory, a local bus, at least one flash-specific DMA controller, including a first flash-specific DMA controller, and a host interface; an intermediate bus coupled to said at least one flash-specific DMA controller; a plurality of semiconductor memory devices, including a first semiconductor memory device; a first flash memory bus coupled to said first semiconductor device; a first flash buffer circuit coupled to said intermediate bus and to said first memory bus; and an adaptability mechanism disposed to transfer data across said intermediate bus at a first data path transfer rate and across said first memory bus at a second data path transfer rate; wherein said intermediate bus comprises a first data path having a first bus width; wherein said intermediate bus comprises an interface data throughput that is defined by said first bus width, a first clock frequency of said intermediate bus, a second clock frequency of said first flash memory bus, an intermediate bus frequency factor which is a quotient of said first clock frequency and said second clock frequency, a selected data sampling rate, and a first strobe frequency of a first strobe signal wherein said selected data sampling rate permits a sampling of data on one edge of the first strobe signal per each strobe signal clock period or on two edges of the first strobe signal per each strobe signal clock period; wherein said interface data throughput of said intermediate bus is defined by a multiplication of said first bus width, said intermediate bus frequency factor, said second clock frequency, and said selected data sampling rate. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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Specification