Methods, systems, and computer program product for implementing three-dimensional integrated circuit designs

• US 10,133,841 B1
• Filed: 09/30/2016
• Issued: 11/20/2018
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Majumder, Chayan, Ginetti, Arnold, Manglani, Chandra Prakash, Kumar, Amit
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US15/282,792
• Time in Patent Office: 781 Days
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

Claims

1. A computer implemented method for implementing three-dimensional or multi-layer integrated circuit designs, comprising:

identifying, with one or more connectivity modules including or coupled with at least one micro-processor of a computing system, an electronic design and a plurality of inputs for implementing connectivity for the electronic design;

reducing at least one first data structures storing the electronic design to at least one first reduced data structure based at least in part upon an identification of an interface portion between at least two layers in the electronic design;

reducing the at least one first reduced data structure into at least one second reduced data structure at least by performing one or more net distribution analyses that generate net distribution analysis results; and

implementing the connectivity between multiple layers in the electronic design at least by assigning a bump in a bump array in the second reduced electronic design to a net connecting a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

2. The computer implemented method of claim 1, identifying the plurality of inputs further comprising:

identifying a first IC (integrated circuit) die design, a second IC die design, a plurality of nets, and the bump array;

identifying a first net from the plurality of nets;

identifying a first terminal in the first IC die design based in part or in whole upon inter-die connectivity for the first net; and

identifying a second terminal in the second IC die design based in part or in whole upon inter-die connectivity for the first net.

3. The computer implemented method of claim 2, identifying the plurality of inputs further comprising:

determining a first bounding box for the first terminal based in part or in whole upon first intra-die connectivity for the first terminal and a second bounding box for the second terminal based in part or in whole upon second intra-die connectivity for the second terminal.

4. The computer implemented method of claim 3, determining the first bounding box comprising:

identifying the first intra-die connectivity for the first terminal;

determining one or more first logic pins and one or more first nets corresponding to the first terminal from the first intra-die connectivity; and

determining the first bounding box for the first terminal based in part or in whole upon the one or more first logic pins and the one or more first nets.

5. The computer implemented method of claim 4, determining the second bounding box comprising:

identifying the second intra-die connectivity for the second terminal;

determining one or more second logic pins and one or more second nets corresponding to the second terminal from the second intra-die connectivity; and

determining the second bounding box for the second terminal based in part or in whole upon the one or more second logic pins and the one or more second nets.

6. The computer implemented method of claim 5, determining the first bounding box and the second bounding box comprising:

arranging the first bounding box and the second bounding box in a single design space; and

identifying information about the bump array into the single design space.

7. The computer implemented method of claim 1, generating the net distribution analysis results by performing the one or more net distribution analyses comprising:

identifying a single design space including the first bounding box, the second bounding box, and information about the bump array, wherein the information about the bump array comprises geometric information of a plurality of bumps in the bump array or a plurality of bump pads corresponding to the plurality of bumps;

identifying a first net interconnecting a first electronic design in the electronic design and a second electronic design in the electronic design;

identifying a first terminal or a first logic pin corresponding to the first terminal for the first net;

identifying a second terminal or a second logic pin corresponding to the second terminal for the first net; and

identifying one or more candidate bumps or one or more candidate bump pads for the first net.

8. The computer implemented method of claim 7, generating the net distribution analysis results by performing the one or more net distribution analyses comprising:

determining respective first aggregated costs for the first net routed through the one or more candidate bumps or the one or more candidate bump pads for the first net; and

determining a first bump or a first bump pad from the one or more candidate bumps or the one or more candidate bump pads based in part or in whole upon the respective first aggregated costs.

9. The computer implemented method of claim 8, generating the net distribution analysis results by performing the one or more net distribution analyses comprising at least one of:

filtering out one or more second bumps from the plurality of bumps or the plurality or one or more bump pads from the plurality of bump pads based in part or in whole upon the respective first aggregated costs;

filtering out one or more first bumps from the bump array based in part or in whole upon congestion analysis results;

or

ignoring or excluding design data pertaining to inter-die interconnects between the first electronic design and the second electronic design in the electronic design.

10. The computer implemented method of claim 1, assigning a bump in the bump array to the net comprising:

identifying a first bump for the net from the net distribution analysis results;

determining whether the first bump has been assigned;

identifying the first bump to the bump in the bump array when the first bump is determined not to have been assigned; and

assigning the bump to the first net when the first bump is determined not to have been assigned.

11. The computer implemented method of claim 10, assigning a bump in the bump array to the net further comprising:

identifying a second net to which the first bump has been assigned when the first bump is determined to have been assigned;

identifying the net distribution results pertaining to the second net; and

identifying one or more first candidate bumps for the first net and one or more second candidate bumps for the second net.

12. The computer implemented method of claim 11, assigning a bump in the bump array to the net further comprising:

determining a first aggregated cost for assigning the first bump to the first net;

determining a second aggregated cost for assigning the first bump to the second net; and

determining whether the first aggregated cost is less than the second aggregated cost.

13. The computer implemented method of claim 12, assigning a bump in the bump array to the net further comprising:

identifying a first candidate bump for the first net when the first aggregated cost is determined not to be less than the second aggregated cost; and

assigning the first candidate bump to the first net when the first aggregated cost is determined not to be less than the second aggregated cost.

14. The computer implemented method of claim 12, assigning a bump in the bump array to the net further comprising:

identifying a second candidate bump for the second net when the first aggregated cost is determined to be less than the second aggregated cost;

dissociating the first bump with the second net;

assigning the second candidate bump to the second net; and

assigning the first bump to the first net.

15. A system for implementing three-dimensional or multi-layer integrated circuit designs, comprising:

a plurality of modules, at least one of which comprises at least one microprocessor including one or more processor cores executing one or more threads in a computing system;

a non-transitory computer accessible storage medium storing thereupon program code that includes a sequence of instructions that, when executed by the at least one micro-processor or processor core of a computing system, causes the at least one micro-processor or processor core at least to;

identify, with one or more connectivity modules including or coupled with at least one micro-processor of a computing system, an electronic design and a plurality of inputs for implementing connectivity for the electronic design;

reduce the electronic design to a first reduced electronic design based at least in part upon an identification of an interface portion between at least two layers in the electronic design;

reduce the first reduced electronic design into a second reduced electronic design at least by performing one or more net distribution analyses that generate net distribution analysis results; and

implement the connectivity between multiple layers in the electronic design at least by assigning a bump in a bump array in the second reduced electronic design to a net connecting a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

16. The system of claim 15, wherein the program code includes further instructions that, when executed by the at least one micro-processor or processor core, cause the at least one processor or processor core to:

identify a single design space including the first bounding box, the second bounding box, and information about the bump array, wherein the information about the bump array comprises geometric information of a plurality of bumps in the bump array or a plurality of bump pads corresponding to the plurality of bumps;

identify a first net interconnecting a first electronic design in the electronic design and a second electronic design in the electronic design;

identify a first terminal or a first logic pin corresponding to the first terminal for the first net;

identify a second terminal or a second logic pin corresponding to the second terminal for the first net; and

identify one or more candidate bumps or one or more candidate bump pads for the first net.

17. The system of claim 16, wherein the program code includes further instructions that, when executed by the at least one micro-processor or processor core, cause the at least one processor or processor core to:

determine respective first aggregated costs for the first net routed through the one or more candidate bumps or the one or more candidate bump pads for the first net; and

determine a first bump or a first bump pad from the one or more candidate bumps or the one or more candidate bump pads based in part or in whole upon the respective first aggregated costs.

18. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for implementing three-dimensional or multi-layer integrated circuit designs, the set of acts comprising:

identifying, with one or more connectivity modules including or coupled with at least one micro-processor of a computing system, an electronic design and a plurality of inputs for implementing connectivity for the electronic design;

reducing the electronic design to a first reduced electronic design based at least in part upon an identification of an interface portion between at least two layers in the electronic design;

reducing the first reduced electronic design into a second reduced electronic design at least by performing one or more net distribution analyses that generate net distribution analysis results; and

implementing the connectivity between multiple layers in the electronic design at least by assigning a bump in the second reduced electronic design in a bump array to a net connecting a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

19. The article of manufacture of claim 18, the set of acts further comprising:

identifying a first bump for the net from the net distribution analysis results;

determining whether the first bump has been assigned;

identifying the first bump to the bump in the bump array when the first bump is determined not to have been assigned;

assigning the bump to the first net when the first bump is determined not to have been assigned;

determining a first aggregated cost for assigning the first bump to the first net;

determining a second aggregated cost for assigning the first bump to the second net; and

determining whether the first aggregated cost is less than the second aggregated cost.

20. The article of manufacture of claim 19, the set of acts further comprising:

identifying a first candidate bump for the first net when the first aggregated cost is determined not to be less than the second aggregated cost;

assigning the first candidate bump to the first net when the first aggregated cost is determined not to be less than the second aggregated cost;

identifying a second candidate bump for the second net when the first aggregated cost is determined to be less than the second aggregated cost;

dissociating the first bump with the second net;

assigning the second candidate bump to the second net; and

assigning the first bump to the first net.