Integrated display system

• US 10,134,325 B2
• Filed: 12/08/2015
• Issued: 11/20/2018
• Est. Priority Date: 12/08/2014
• Status: Active Grant

• Current Assignee: Aledia
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, Gholamreza, Azizi, Yaser
• Primary Examiner(s): Shah, Priyank
• Application Number:
  US14/961,983
• Publication Number:
  US 20160163253A1
• Time in Patent Office: 1,078 Days
• CPC Class Codes: G09G 2300/0828 forming a digital to analog [D/A] conversion circuit
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2096 Details of the interface to the display terminal specific for a flat panel suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element

Abstract

What is disclosed are systems and methods for emissive display systems constructed on integrated architecture platforms, for which the pixels are smart and can behave differently under different conditions to save power, provide better image quality, and/or conserve their value to reduce the power consumption associated with programming.

Claims

1. A display system comprising:

a plurality of pixels each capable of at least a first mode of operation and a second mode of operation, each pixel comprising;

a light-emitting device;

a light-emitting device driver for driving the light-emitting device to emit light;

a digital memory including a shift register for storing data comprising greyscale data for display by the pixel, the shift register having an output coupled to the light-emitting device driver for controlling the driving of the light-emitting device, the greyscale data stored in the shift register shifted by a bit in response to each clock signal of a time division clock input to the pixel, the time division clock including different clock signal periods corresponding to the different weights of the bits of the greyscale data; and

a controller operative to allow storage of incoming data to the digital memory in the first mode of operation and to preserve data in the digital memory in the second mode of operation.

2. The display system of claim 1, wherein the plurality of pixels are arranged into at least one row, and wherein a plurality of shift registers of pixels in the at least one row are chained together into a shift register chain, wherein incoming data loaded to the shift register chain includes only data for pixels in the first mode of operation, and wherein controllers of pixels in the second mode of operation cause the incoming data to bypass the pixels in the second mode of operation.

3. The display system of claim 1 wherein during a time of a frame the light-emitting device driver drives the light-emitting device for a total time determined by the data in the digital memory of the pixel according to the output of the shift register controlling the driving of the light-emitting device as shifted by the time division clock.

4. The display system of claim 1 wherein during a frame, for each bit of the greyscale data stored in each pixel, the light-emitting device driver of the pixel drives the light-emitting device of the pixel in one of an on-state and an off-state corresponding to a value of the bit for a time period corresponding to a weight of the bit, the light-emitting device driver driving the light emitting-device in accordance with said time division clock signals.

5. The display system of claim 1 wherein the digital memory is operative for storing data comprising first greyscale data and second greyscale data, wherein the controller is operative to allow storage of incoming data comprising incoming first greyscale data simultaneously with the pixel'"'"'s displaying of the second greyscale data.

6. The display system of claim 1 wherein each pixel comprises an enable digital memory for storing a value determining one of the first mode of operation or the second mode of operation for the pixel.

7. The display system of claim 1 wherein each greyscale bit of the incoming data are loaded into the digital memory of pixels in a row and displayed prior to a loading of a next greyscale bit.

8. The display system of claim 1 wherein the shift register of each pixel comprises a rotating shift register.

9. The display system of claim 1 wherein the light-emitting device driver drives the light-emitting device at a driving force based upon at least one of a peak brightness condition, a weight of a bit of the greyscale data being displayed, and a group of bits of the greyscale data.

10. The display system of claim 1 wherein the light-emitting device driver drives the light-emitting device with use of at least one of a plurality of bias voltages and a plurality of current sources.

11. The display system of claim 1 wherein the light-emitting device driver comprises a multiplexer with weighted select line timing for programming and retrieving data from the digital memory which comprises latches.

12. The display system of claim 1 wherein each pixel is capable of a high dynamic range mode for which the pixel may be driven at one of a plurality of different biasing points in accordance with one of a plurality of biasing conditions for that pixel.

13. The display system of claim 1 wherein the different clock signal periods corresponding to the different weights of the bits of the greyscale data are non-linear in accordance with a non-linear gamma curve.

14. The display system of claim 1 wherein each pixel is capable of a further test mode of operation and comprises a test circuit to control driving of the light-emitting device, wherein when the pixel is in test mode the test circuit drives the light-emitting device independent of the digital memory.

15. The display system of claim 1 wherein each pixel is capable of a low power mode for which the greyscale data for display by the pixel constitutes a subportion of a total greyscale data stored in the digital memory.

16. The display system of claim 1 wherein the weight of each bit of the greyscale data is assigned dynamically.

17. The display system of claim 1 wherein the time division clock is passed from an originating pixel row to a receiving pixel row including a delay to synchronize the time division clock received by the receiving pixel row with an end of programming of the receiving pixel row.

18. The display system of claim 1 wherein each weight of each greyscale bit corresponds to the bit order i of the greyscale bit, and the time period corresponding to a bit of weight i is proportional to 2ⁱ.