Scanning acoustic microscope sensor array for chip-packaging interaction package reliability monitoring

• US 10,134,649 B2
• Filed: 01/06/2016
• Issued: 11/20/2018
• Est. Priority Date: 01/06/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Davis, Taryn J., Fry, Jonathan R., Sinha, Tuhin
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US14/988,893
• Publication Number:
  US 20170194221A1
• Time in Patent Office: 1,049 Days
• Field of Search: 438 14- 16
• CPC Class Codes: G01N 2291/101 one transducer
• CPC Class Codes: G01N 2291/2697 Wafer or (micro)electronic parts
• CPC Class Codes: G01N 29/043 in the interior, e.g. by shear waves
• CPC Class Codes: G01N 29/06 Visualisation of the interior, e.g. acoustic microscopy medical or veterinary diagnosis using sonic waves A61B8/00; representation of acoustic wave distribution G01H3/125, G01H9/002; short-range imaging systems using reflection of acoustic waves G01S15/8906
• CPC Class Codes: G01N 29/0681 by acoustic microscopy, e.g. scanning acoustic microscopy
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating

Abstract

A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate; sensing chip-packaging interaction failure in the underfilled flip-chip module in situ; reporting in-situ chip-packaging interaction failure to a device in real-time; and imaging the chip-packaging interaction failure with an indirect scanning acoustic microscope.

Claims

1. A method, comprising:

forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate;

sensing chip-packaging interaction failure in the underfilled flip-chip module in situ;

reporting in-situ chip-packaging interaction failure to a device processor in real-time; and

imaging the chip-packaging interaction failure with an indirect scanning acoustic microscope;

wherein the sensing is performed with a sensor embedded in a portion of the flip-chip module.

2. The method of claim 1, further comprising mitigating the chip-packaging interaction failure before catastrophic failure of the flip-chip module by reworking the package to remove the failed components of the flip-chip module.

3. The method of claim 1, wherein the reporting and imaging of the chip-packaging interaction failure occurs in real time.

4. A method, comprising:

forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate;

sensing chip-packaging interaction failure in the underfilled flip-chip module;

reporting in-situ chip-packaging interaction failure to a device processor; and

imaging the chip-packaging interaction failure with the device processor, wherein the sensing is performed with a sensor embedded in a portion of the flip-chip module.

5. The method of claim 4, wherein the sensor feeds data to a scanning system.

6. The method of claim 4, wherein the sensor includes an array of sensors disposed in a corner region of the flip-chip module.

7. The method of claim 4, wherein the sensor includes an array of sensors disposed in a portion of the underfill material, outside the underfill material, or a combination comprising at least one of the foregoing.

8. The method of claim 4, wherein the substrate comprises an organic material, a ceramic material, or a combination comprising at least one of the foregoing.

9. The method of claim 4, wherein the underfill material is thermoplastic material, a thermoset material, an epoxy material, or a combination comprising at least one of the foregoing.

10. The method of claim 4, wherein the flip-chip module further includes a ball grid array.

11. The method of claim 4, wherein the flip-chip module further includes a cover disposed over the flip-chip module, opposite the substrate.

12. The method of claim 4, wherein the data provided includes spatial data and temporal data.

13. The method of claim 12, wherein the spatial data includes location and type of fails and wherein the temporal data includes propagation of fails and first cause.

14. The method of claim 4, wherein the reporting and imaging are non-destructive to the flip-chip module.

15. The method of claim 4, further comprising mitigating the chip-packaging interaction failure before catastrophic failure of the flip-chip module.

16. The method of claim 4, wherein the device includes a scanning acoustic microscope.

17. The method of claim 4, wherein the chip-packaging interaction failure includes mechanical failure or electrical failure.

18. The method of claim 16, wherein the mechanical failure includes underfill sidewall delamination and back underfill cracking and wherein the electrical failure includes crack propagation in the flip-chip module that severs electrical pathways.

19. The method of claim 4, wherein the reporting and imaging of the chip-packaging interaction failure occurs in real time.