Cell boundary structure for embedded memory

• US 10,134,748 B2
• Filed: 09/01/2017
• Issued: 11/20/2018
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Ming Chyi, Liu, Shih-Chang, Chen, Sheng-Chieh, Chang, Yu-Hsing
• Primary Examiner(s): Ahmed, Selim
• Application Number:
  US15/694,098
• Publication Number:
  US 20180151579A1
• Time in Patent Office: 445 Days
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region

Abstract

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Claims

1. A method for forming an integrated circuit (IC), the method comprising:

forming an isolation structure in a semiconductor substrate, wherein the isolation structure separates a memory region of the semiconductor substrate from a logic region of the semiconductor substrate;

forming a multilayer film covering the isolation structure, the memory region, and the logic region;

forming a memory cell structure on the memory region, wherein the memory cell structure is formed from the multilayer film;

forming a dummy capping layer covering the memory cell structure and a remainder of the multilayer film;

performing a first etch into the multilayer film and the dummy capping layer to remove the multilayer film and the dummy capping layer from the logic region, such that the multilayer film and the dummy capping layer define a dummy sidewall on the isolation structure;

forming a sidewall spacer layer covering the dummy capping layer, the isolation structure, and the logic region, and further lining the dummy sidewall;

performing a second etch into the sidewall spacer layer to remove horizontal segments of the sidewall spacer layer, and to form a sidewall spacer on dummy sidewall; and

forming a logic device structure on the logic region after forming the sidewall spacer.

2. The method according to claim 1, wherein the dummy capping layer and the sidewall spacer collectively define a boundary sidewall overlying the isolation structure and facing the logic region, wherein the boundary sidewall is slanted, and wherein a portion of the boundary sidewall defined by the dummy capping layer is continuous with a portion of the boundary sidewall defined by the sidewall spacer.

3. The method according to claim 1, wherein the sidewall spacer at least partially defines a boundary sidewall overlying the isolation structure and facing the logic region, wherein the boundary sidewall is homogenous, and wherein the dummy sidewall is heterogenous.

4. The method according to claim 1, wherein the multilayer film comprises an oxide-nitride-oxide (ONO) film, a polysilicon layer overlying the ONO film, and a nitride layer overlying the polysilicon layer, such that the dummy sidewall is defined in part by the ONO film, the polysilicon layer, and the nitride layer.

5. The method according to claim 1, wherein the sidewall spacer has a triangular profile upon completion of the second etch.

6. The method according to claim 1, wherein the dummy sidewall is vertical or substantially vertical, and wherein the dummy sidewall is in direct contact with the sidewall spacer.

7. The method according to claim 1, further comprising:

forming a pad layer covering the semiconductor substrate;

patterning the pad layer with a layout of the isolation structure;

performing a third etch into the semiconductor substrate with the pad layer in place to form an isolation trench in the semiconductor substrate;

filling the isolation trench with a dielectric material to form the isolation structure; and

performing a fourth etch into the pad layer with the sidewall spacer in place to remove the pad layer from the logic region.

8. The method according to claim 7, wherein the sidewall spacer at least partially defines a boundary sidewall overlying the isolation structure and facing the logic region, wherein the dummy sidewall and the pad layer share a material, and wherein the boundary sidewall is devoid of the material.

9. The method according to claim 1, wherein the forming of the logic device structure comprises:

forming a conformal high κ

dielectric layer over the dummy capping layer, the sidewall spacer, and the logic region;

forming a polysilicon layer over the conformal high κ

dielectric layer; and

performing a third etch into the conformal high κ

dielectric layer and the polysilicon layer to form a polysilicon gate electrode and a high κ

gate dielectric layer stacked on the logic region.

10. The method according to claim 9, further comprising:

replacing the polysilicon gate electrode with a metal gate electrode.

11. A method for forming an integrated circuit (IC), the method comprising:

forming an isolation structure in a semiconductor substrate, wherein the isolation structure separates a memory region of the semiconductor substrate from a logic region of the semiconductor substrate, and wherein the isolation structure comprises a dielectric material;

forming an oxide-nitride-oxide (ONO) film covering the semiconductor substrate;

forming a doped polysilicon layer covering the ONO film;

forming a silicon nitride layer covering the doped polysilicon layer;

forming a dummy polysilicon layer covering the silicon nitride layer;

forming a mask over the dummy polysilicon layer so an edge of the mask is directly over the isolation structure;

performing an etch with the mask in place to remove portions of the dummy polysilicon layer, the silicon nitride layer, the doped polysilicon layer, and the ONO film on the logic region, wherein the dummy polysilicon layer, the silicon nitride layer, the doped polysilicon layer, and the ONO film each have a sidewall overlying the isolation structure and aligned to the edge of the mask after performing the etch;

stripping the mask;

conformally depositing a sidewall spacer layer covering the dummy polysilicon layer, the isolation structure, and the logic region, and further lining the sidewall of each of the dummy polysilicon layer, the silicon nitride layer, the doped polysilicon layer, and the ONO film; and

performing an etch back into the sidewall spacer layer to remove horizontal segments of the sidewall spacer layer without removing vertical segments of the sidewall spacer layer, wherein a vertical segment of the sidewall spacer layer defines a sidewall spacer adjoining and sealing the sidewall of each of the dummy polysilicon layer, the silicon nitride layer, the doped polysilicon layer, and the ONO film.

12. The method according to claim 11, wherein the sidewall spacer layer comprises polysilicon.

13. The method according to claim 11, wherein the etch back forms a boundary sidewall defined by the dummy polysilicon layer and the sidewall spacer, and wherein the boundary sidewall overlies the isolation structure and is slanted downward towards the logic region.

14. The method according to claim 11, further comprising:

patterning memory portions respectively of the ONO film, the doped polysilicon layer, and the silicon nitride layer to form a control gate stack on the memory region.

15. The method according to claim 11, further comprising:

forming a memory cell structure on the memory region before the etch back; and

forming a logic device structure on the logic region after the etch back.

16. A method for forming an integrated circuit (IC), the method comprising:

forming an isolation structure in a semiconductor substrate, wherein the isolation structure demarcates a memory region of the semiconductor substrate and a logic region of the semiconductor substrate;

forming a multilayer film covering the isolation structure, the memory region, and the logic region;

performing an etch into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure; and

forming a sidewall spacer overlying the isolation structure and lining the dummy sidewall, wherein the sidewall spacer has a memory-facing sidewall bordering the dummy sidewall, and further has a logic-facing sidewall angled downward from the memory-facing sidewall to the isolation structure.

17. The method according to claim 16, further comprising:

forming a logic device structure on the logic region after forming the sidewall spacer.

18. The method according to claim 16, further comprising:

forming a memory cell structure on the memory region, wherein the memory cell structure is formed partially from the multilayer film before the etch.

19. The method according to claim 16, wherein the sidewall spacer at least partially defines a slanted sidewall facing the logic region.

20. The method according to claim 16, further comprising:

forming a dummy capping layer covering the multilayer film, wherein a top surface of the isolation structure is elevated relative to a bottom surface of the dummy capping layer, and wherein the etch is also performed into the dummy capping layer, such that the dummy capping layer and the multilayer film at least partially define the dummy sidewall.