Method of processing a substrate and a device manufactured by using the method

• US 10,134,757 B2
• Filed: 06/30/2017
• Issued: 11/20/2018
• Est. Priority Date: 11/07/2016
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Chun, Seung Ju, Yoo, Yong Min, Choi, Jong Wan, Kim, Young Jae, Kim, Sun Ja, Lim, Wan Gyu, Min, Yoon Ki, Lee, Hae Jin, Yoo, Tae Hee
• Primary Examiner(s): Payen, Marvin
• Assistant Examiner(s): Joy, Jeremy
• Application Number:
  US15/640,239
• Publication Number:
  US 20180130701A1
• Time in Patent Office: 508 Days
• CPC Class Codes: C23C 16/345 Silicon nitride
• CPC Class Codes: C23C 16/4554 Plasma being used non-continuously in between ALD reactions C23C16/56 takes precedence
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

Claims

1. A method of processing a substrate, the method comprising:

stacking a stacked structure including a silicon oxide layer and a first silicon nitride layer a plurality of number of times;

forming a second silicon nitride layer on the first silicon nitride layer;

forming a third silicon nitride layer on the second silicon nitride layer;

densifying the third silicon nitride layer;

wet-etching at least a portion of a sacrificial word line structure including the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer;

forming an interlayer insulation layer on the sacrificial word line structure;

removing the sacrificial word line structure; and

forming a conductive word line structure corresponding to a space from which the sacrificial word line structure has been removed.

2. The method of claim 1, wherein, in the wet-etching of at least a portion of the sacrificial word line structure, an etch rate of the third silicon nitride layer is less than an etch rate of the second silicon nitride layer.

3. The method of claim 1, further comprising:

etching the stacked structure before forming a second silicon nitride layer on the first silicon nitride layer to form a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface.

4. The method of claim 3, wherein, in the wet-etching of at least a portion of the sacrificial word line structure, an etch rate of a portion of the third silicon nitride layer on the side surface is greater than an etch rate of portions of the third silicon nitride layer on the upper and lower surfaces.

5. The method of claim 3, wherein the wet-etching of at least a portion of the sacrificial word line structure comprises:

exposing a portion of the second silicon nitride layer formed on the side surface by removing a portion of the third silicon nitride layer formed on the side surface; and

exposing a portion of the silicon oxide layer formed on the side surface by removing the second silicon nitride layer.

6. The method of claim 5, wherein the exposing of the portion of the second silicon nitride layer and the exposing of the portion of the silicon oxide layer are performed via a single etch process.

7. The method of claim 5, wherein the exposing of the portion of the second silicon nitride layer and the exposing of the portion of the silicon oxide layer are performed without performing a photolithographic process.

8. The method of claim 1, wherein a hydrogen-containing nitrogen gas is used in the forming of the second silicon nitride layer.

9. The method of claim 1, wherein, a hydrogen-free nitrogen gas is used in the forming of the third silicon nitride layer.

10. The method of claim 1, wherein a flow rate of a hydrogen-containing nitrogen gas used in the forming of the third silicon nitride layer is less than a flow rate of a hydrogen-containing nitrogen gas used in the forming of the second silicon nitride layer.

11. The method of claim 1, wherein a hydrogen content of the third silicon nitride layer is less than a hydrogen content of the second silicon nitride layer.

12. The method of claim 1, wherein the densifying is performed via an asymmetric plasma process.

13. The method of claim 12, wherein, a gas including at least one of argon (Ar) and nitrogen is used during the asymmetric plasma process.

14. The method of claim 1, wherein a nitrogen content of the third silicon nitride layer is greater than a nitrogen content of the second silicon nitride layer.

15. The method of claim 1, wherein the conductive word line structure comprises:

a first conductive layer extending toward a channel;

a second conductive layer on the first conductive layer; and

a third conductive layer on the second conductive layer; and

the second conductive layer and the third conductive layer have different sidewall profiles.

16. The method of claim 15, wherein

the first conductive layer comprises a groove, and

the groove is formed adjacent to the second conductive layer.

17. The method of claim 15, wherein, with respect to one side surface of the second conductive layer and the third conductive layer, one end of the third conductive layer protrudes from a side surface of the second conductive layer.

18. The method of claim 17, wherein, with respect to another side surface of the second conductive layer and the third conductive layer, one end of the second conductive layer protrudes from a side surface of the third conductive layer or vice versa.

19. A method of processing a substrate, the method comprising:

stacking a stacked structure including an insulation layer and a first sacrificial layer a plurality of number of times;

etching the stacked structure to form a stepped structure on the stacked structure;

forming a second sacrificial layer on the first sacrificial layer;

forming a third sacrificial layer on the second sacrificial layer;

densifying the third sacrificial layer;

etching at least a portion of a sacrificial word line structure including the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer;

forming an interlayer insulation layer on the sacrificial word line structure;

removing the sacrificial word line structure; and

forming a conductive word line structure corresponding to the sacrificial word line structure.

20. A method of processing a substrate, the method comprising:

forming a first silicon nitride layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface;

forming a second silicon nitride layer on the first silicon nitride layer;

selectively densifying the second silicon nitride layer; and

performing a wet etching process on the first silicon nitride layer and the second silicon nitride layer,

wherein, during the wet etching process, an etch rate of a portion of a nitride layer on the side surface is greater than an etch rate of portions of a nitride layer on the upper and lower surfaces.

21. A method of processing a substrate, the method comprising:

forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface;

selectively densifying, via asymmetric plasma application, portions of the at least one layer respectively on the upper surface and the lower surface except for the side surface; and

performing an isotropic etching process on the at least one layer,

wherein, during the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.