Gate top spacer for finFET

• US 10,134,763 B2
• Filed: 12/31/2017
• Issued: 11/20/2018
• Est. Priority Date: 08/09/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Basker, Veeraraghavan S., Gluschenkov, Oleg, Mochizuki, Shogo, Reznicek, Alexander
• Primary Examiner(s): Trinh, Michael
• Application Number:
  US15/859,557
• Publication Number:
  US 20180145092A1
• Time in Patent Office: 324 Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

The capacitance between gate structures and source/drain contacts of FinFET devices is reduced by the incorporation of inner spacers in the top portions of the gate structures. A replacement metal gate process used in the fabrication of such devices includes formation of the inner spacers following partial removal of dummy gate material. The remaining dummy gate material is then removed and replaced with gate dielectric and metal gate material.

Claims

1. A fabrication method, comprising:

obtaining a monolithic structure including a plurality of parallel semiconductor fins, a dummy gate on the semiconductor fins, and sidewall spacers on the dummy gate;

partially removing the dummy gate to form a recess between the sidewall spacers and above a remaining portion of the dummy gate;

forming inner spacers within the recess and on the sidewall spacers;

removing the remaining portion of the dummy gate, thereby exposing a channel portion of the semiconductor fin and forming spaces beneath the inner spacers;

forming a gate dielectric layer within the recess and the spaces and on the channel portion of the semiconductor fin;

forming a barrier layer on the gate dielectric layer, and

filling the recess and spaces with electrically conductive gate material.

2. The method of claim 1, further including forming a plurality of FinFET devices using one or more of the plurality of parallel semiconductor fins.

3. The method of claim 1, further including forming the inner spacers from a material having a dielectric constant of less than 3.9.

4. The method of claim 1, further including:

recessing the electrically conductive gate material, and

forming a dielectric cap on the recessed electrically conductive gate material.

5. The method of claim 4, further including:

removing portions of the dielectric cap and the gate dielectric layer in a gate contact area, and

forming an electrically conductive contact on the electrically conductive gate material in the gate contact area.

6. The method claim 4, wherein the electrically conductive gate material comprises tungsten.

7. The method of claim 4, wherein the remaining portion of the dummy gate has a height dimension of ten to twenty nanometers.

8. The method of claim 1, wherein the semiconductor fins consist essentially of monocrystalline silicon or monocrystalline silicon germanium.

9. The method of claim 1, wherein the sidewall spacers comprise a first dielectric material and the inner spacers comprise a second dielectric material, the second dielectric material having a dielectric constant below 3.9 and the first dielectric material having a dielectric constant greater than 3.9.

10. The method of claim 1, wherein filling the recess and spaces with electrically conductive gate material further includes forming a metal gate structure having a top portion between the inner spacers and a bottom portion, the top portion having a smaller width dimension and a greater height dimension than the bottom portion of the metal gate structure.

11. The method of claim 10, further including forming the inner spacers from a material having a dielectric constant of less than 3.9.