Array substrate, method of manufacturing the same, and display device

• US 10,134,786 B2
• Filed: 04/21/2014
• Issued: 11/20/2018
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Yoo, Seongyeol, Choi, Seungjin, Kim, Heecheol, Song, Youngsuk
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): Culbert, Christopher
• Application Number:
  US14/421,947
• Publication Number:
  US 20160027817A1
• Time in Patent Office: 1,674 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

Disclosed is an array substrate, a method of manufacturing the same, and a display device. The method of manufacturing an array substrate includes: forming a pattern comprising an active layer, a source, a drain, a data line and a pixel electrode on a base substrate through a single patterning process; forming a pattern of an insulating layer; forming a pattern comprising a gate and a gate line through a single patterning process. In the array substrate, the method of manufacturing the same, and the display device of the present invention, only two patterning processes are required to achieve the fabrication of the array substrate, which has less and simple process steps, thereby reduces the manufacturing complexity and manufacturing cost, and increasing the production efficiency and the economic benefit.

Claims

1. A method of manufacturing an array substrate, comprising:

forming a pattern comprising an active layer, a source, a drain, a data line and a pixel electrode on a base substrate through a single patterning process by using a single mask;

forming a pattern of an insulating layer; and

forming a pattern comprising a gate and a gate line through a single patterning process,

wherein forming a pattern comprising an active layer, a source, a drain, a data line and a pixel electrode on a base substrate through a single patterning process comprises;

forming a semiconductor film on the base substrate;

coating a photoresist on the semiconductor film, exposing the photoresist with a dual tone mask and developing to completely remain the photoresist corresponding to an active layer region, to partially remain the photoresist corresponding to regions of the source, the drain, the data line and the pixel electrode, and to completely remove the photoresist in remaining regions so as to expose the semiconductor film;

etching the exposed semiconductor film;

ashing the photoresist to thin the photoresist corresponding to the active layer region and to expose the semiconductor film in regions other than the active layer region;

transforming the exposed semiconductor film into a conductor by plasma processing to form the pattern comprising the active layer, the source, the drain, the data line and the pixel electrode; and

removing residual photoresist.

2. The method of claim 1, wherein forming a pattern comprising a gate and a gate line through a single patterning process further comprises:

forming a pattern comprising a common electrode line and a comb-shaped common electrode.

3. The method of claim 2, wherein forming a pattern comprising a gate and a gate line and a pattern comprising a comb-shaped common electrode and a common electrode line through a single patterning process comprises:

forming a transparent conductive film and a metal film in this order over the insulating layer;

coating a photoresist on the metal film, exposing the photoresist with a dual tone mask and developing to completely remain the photoresist corresponding to regions of the gate, the gate line and the common electrode line, to partially remain the photoresist corresponding to a comb-shaped common electrode region, and completely remove the photoresist in remaining regions so as to expose the metal film;

etching the exposed metal film and the transparent conductive film underlying the exposed metal film;

ashing the photoresist to thin the photoresist corresponding to the regions of the gate, the gate line and the common electrode line and expose the metal film in regions other than the regions of the gate, the gate line and the common electrode line;

etching the exposed metal film; and

removing residual photoresist to form the pattern comprising the gate, the gate line, the common electrode line and the comb-shaped common electrode.

4. The method of claim 1, wherein the pixel electrode is comb-shaped.

5. The method of claim 1, wherein a material for the semiconductor film comprises at least one of indium gallium zinc oxide, indium gallium tin oxide, or indium tin oxide.