Multi-gate device and method of fabrication thereof

• US 10,134,843 B2
• Filed: 05/19/2017
• Issued: 11/20/2018
• Est. Priority Date: 01/13/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, I-Sheng, Yeh, Chih Chieh, Wu, Cheng-Hsien, Yeo, Yee-Chia
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/600,441
• Publication Number:
  US 20170256615A1
• Time in Patent Office: 550 Days
• Field of Search: 257192, 257327, 257401, 257E29022, 257E29128, 257E29345, 257E21409, 438283, 438478
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Claims

1. A semiconductor device, comprising:

a fin extending from a substrate, the fin having a source/drain region and a channel region, wherein the channel region includes;

a first semiconductor layer;

a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area extending from a top surface of the first semiconductor layer to a bottom surface of the second semiconductor layer;

a third semiconductor layer including silicon at least partially wrapping around the second semiconductor layer;

a high-k dielectric layer at least partially wrapping around the first semiconductor layer and the second semiconductor layer; and

a metal layer formed along opposing sidewalls of the high-k dielectric layer,

wherein the metal layer includes a first material, and

wherein the spacing area is free of the first material.

2. The semiconductor device of claim 1, wherein each of the first and second semiconductor layers has a rounded profile.

3. The semiconductor device of claim 2, wherein the rounded profile has a circle shape.

4. The semiconductor device of claim 1, wherein the second semiconductor layer includes at least one of silicon germanium and germanium.

5. The semiconductor device of claim 1, wherein the channel region further includes:

a fourth semiconductor layer disposed between the first and second semiconductor layers,

wherein a top surface of the fourth semiconductor layer interfaces at least a portion of the bottom surface of the second semiconductor layer; and

wherein a bottom surface of the fourth semiconductor layer interfaces at least a portion of the top surface of the first semiconductor layer.

6. The semiconductor device of claim 5, wherein the fourth semiconductor layer includes silicon germanium oxide.

7. The semiconductor device of claim 1, wherein the third semiconductor layer has a thickness between 0.5 nm and 2 nm.

8. A semiconductor device, comprising:

a fin extending from a substrate, wherein a channel region of the fin includes;

a first semiconductor layer;

a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area;

a third semiconductor layer including silicon at least partially wrapping around the second semiconductor layer;

an interposing feature including;

a first portion of a continuous first material layer at least partially wrapping around the first semiconductor layer;

a second portion of the continuous first material layer at least partially wrapping around the second semiconductor layer; and

a metal layer formed along opposing sidewalls of the interposing feature in the channel region, wherein the spacing area is free of the metal layer.

9. The semiconductor device of claim 8, wherein each of the first and second semiconductor layers has a rounded profile.

10. The semiconductor device of claim 8, wherein the second semiconductor layer includes at least one of silicon germanium and germanium.

11. The semiconductor device of claim 8, wherein a thickness of the first semiconductor layer is less than twice of a width of the interposing feature.

12. The semiconductor device of claim 8, wherein the channel region further includes:

a fourth semiconductor layer disposed between the first and second semiconductor layers,

wherein a top surface of the fourth semiconductor layer interfaces a bottom surface of the second semiconductor layer; and

wherein a bottom surface of the fourth semiconductor layer interfaces a top surface of the first semiconductor layer.

13. The semiconductor device of claim 12, wherein the fourth semiconductor layer includes silicon germanium oxide.

14. The semiconductor device of claim 9, wherein the rounded profile is selected from the group consisting of a rounded square, a circle, and an oval.

15. A semiconductor device, comprising:

a fin element extending from a substrate, wherein a channel region of the fin element includes;

a first semiconductor layer;

a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area;

a third semiconductor layer disposed between the first and second semiconductor layers, wherein a top surface of the third semiconductor layer interfaces a bottom surface of the second semiconductor layer; and

wherein a bottom surface of the third semiconductor layer interfaces a top surface of the first semiconductor layer;

a fourth semiconductor layer including silicon at least partially wrapping around the second semiconductor layer;

a high-k dielectric layer at least partially wrapping around the first, second, and third semiconductor layers; and

a metal layer formed along opposing sidewalls of the high-k dielectric layer,

wherein the metal layer includes a scavenging material, and

wherein the spacing area is free of the scavenging material.

16. The semiconductor device of claim 15, wherein each of the first and second semiconductor layers has a rounded profile.

17. The semiconductor device of claim 16, wherein the rounded profile has a rounded square shape.

18. The semiconductor device of claim 15, wherein the second semiconductor layer includes at least one of silicon germanium and germanium.

19. The semiconductor device of claim 15, wherein the third semiconductor layer includes silicon germanium oxide.

20. The semiconductor device of claim 15, wherein the scavenging material includes at least one of titanium, hafnium, zirconium, tantalum, titanium nitride, tantalum nitride, tantalum silicon nitride, and titanium silicon nitride.