FinFET structures and methods of forming the same

• US 10,134,847 B2
• Filed: 05/08/2017
• Issued: 11/20/2018
• Est. Priority Date: 06/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Chih Chieh, Peng, Cheng-Yi, Lee, Tsung-Lin
• Primary Examiner(s): Vu, David
• Application Number:
  US15/589,788
• Publication Number:
  US 20170243941A1
• Time in Patent Office: 561 Days
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer.

Claims

1. A structure comprising:

a first transistor comprising;

a first channel region comprising alternating first semiconductor layers and second semiconductor layers above a substrate, each of the first semiconductor layers being separated from neighboring ones of the first semiconductor layers, each of the first semiconductor layers in the first channel region having a first sidewall and a second sidewall, the first sidewalls being aligned along a first plane extending perpendicularly to the substrate, the second sidewalls being aligned along a second plane extending perpendicularly to the substrate, sidewalls of the second semiconductor layers in the first channel region being between the first plane and the second plane;

a first source/drain region and a second source/drain region disposed on opposite sides of the first channel region, each of the first semiconductor layers extending from the first source/drain region to the second source/drain region;

a first dielectric layer contacting the first sidewalls and the second sidewalls of the first semiconductor layers, the first dielectric layer extending into a region between the first plane and the second plane; and

a first gate electrode over the first dielectric layer; and

a second transistor comprising;

a second channel region comprising the alternating first semiconductor layers and second semiconductor layers above the substrate, each of the second semiconductor layers in the second channel region having a third sidewall and a fourth sidewall, the third sidewalls being aligned along a third plane, the fourth sidewalls being aligned along a second plane, sidewalls of the first semiconductor layers in the second channel region being between the third plane and the fourth plane;

a third source/drain region and a fourth source/drain region disposed on opposite sides of the second channel region, each of the first semiconductor layers extending from the third source/drain region to the fourth source/drain region;

a second dielectric layer contacting the third sidewalls and the fourth sidewalls of the first semiconductor layers; and

a second gate electrode over the second dielectric layer.

2. The structure of claim 1, wherein each of the first semiconductor layers have a top surface and a bottom surface, the first dielectric layer contacting the top surfaces and the bottom surfaces of the first semiconductor layers.

3. The structure of claim 2, wherein each of the first semiconductor layers is compressively strained.

4. The structure of claim 2, wherein each of the first semiconductor layers is tensilely strained.

5. The structure of claim 1, wherein each of the second semiconductor layers has a notched lateral side having a surface of a crystalline plane, the notched lateral sides extending between the first plane and the second plane.

6. The structure of claim 1, wherein each of the second semiconductor layers has a notched lateral side having a surface that is not a crystalline plane, the notched lateral sides extending between the first plane and the second plane.

7. The structure of claim 1, wherein each of the first semiconductor layers is compressively strained, and wherein each of the second semiconductor layers is tensilely strained.

8. The structure of claim 1, wherein each of the first semiconductor layers is tensilely strained, and wherein each of the second semiconductor layers is compressively strained.

9. The structure of claim 1, wherein the first transistor is an n-type transistor.

10. The structure of claim 1, further comprising a buffer layer interposed between a bottommost first semiconductor layer and the substrate.

11. A structure comprising:

an n-type device comprising;

a first channel region comprising a first superlattice, the first superlattice comprising alternating first layers and second layers, the first layers being a first semiconductor material, the second layers being a second semiconductor material, each of the first layers has a first sidewall and a second sidewall in the first channel region, the first sidewalls being aligned along a first plane, the second sidewalls being aligned along a second plane, side surfaces of the second layers being between the first plane and the second plane,

a first source/drain region and a second source/drain region disposed on opposite sides of the first channel region, each of the first layers and the second layers extending from the first source/drain region to the second source/drain region,

a first gate dielectric on the first superlattice, and

a first gate electrode on the first gate dielectric; and

a p-type device comprising;

a second channel region comprising a second superlattice, the second superlattice comprising alternating third layers and fourth layers, the third layers being the first semiconductor material, the fourth layers being the second semiconductor material, the first semiconductor material and the second semiconductor material being ordered in the second superlattice a same order as in the first superlattice, each of the fourth layers has a third sidewall and a fourth sidewall in the second channel region, the third sidewalls being aligned along a third plane, the fourth sidewalls being aligned along a fourth plane, side surfaces of the third layers being between the third plane and the fourth plane,

a third source/drain region and a fourth source/drain region disposed on opposite sides of the second channel region, each of the third layers and the fourth layers extending from the third source/drain region to the fourth source/drain region,

a second gate dielectric on the second superlattice, and

a second gate electrode on the second gate dielectric.

12. The structure of claim 11, wherein each of the first layers and the third layers are compressively strained, and each of the second layers and the fourth layers are tensilely strained.

13. The structure of claim 11, wherein sidewalls of the first layers are recessed from sidewalls of the second layers.

14. The structure of claim 13, wherein sidewalls of the fourth layers are recessed from sidewalls of the third layers.

15. A structure comprising:

a first fin and a second fin extending upwards from a substrate, each of the first fin and the second fin comprising alternating first layers of a first material and second layers of a second material, sidewalls of the second layers in a first channel region of the first fin being recessed from sidewalls of the first layers, sidewalls of the first layers in a second channel region of the second fin being recessed from sidewalls of the first fin;

a first gate dielectric over and extending continuously along sidewalls of the first layer and the second layer in the first channel region;

a second gate dielectric over and extending continuously along sidewalls of the first layer and the second layer in the second channel region;

a first conductive gate over the first gate dielectric; and

a second conductive gate over the second gate dielectric.

16. The structure of claim 15, wherein each of the first layers is compressively strained.

17. The structure of claim 15, wherein each of the first layers is tensilely strained.

18. The structure of claim 15, wherein sidewalls of the second layers are curved.

19. The structure of claim 15, wherein sidewalls of the second layers comprise linear sections.

20. The structure of claim 15, wherein the first channel region is a channel region of an n-type transistor.