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Organic light emitting diode display having thin film transistor substrate using oxide semiconductor

  • US 10,134,877 B2
  • Filed: 04/08/2016
  • Issued: 11/20/2018
  • Est. Priority Date: 07/30/2013
  • Status: Active Grant
First Claim
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1. A method for manufacturing an organic light emitting diode (OLED) display, the method comprising:

  • forming a gate electrode on a substrate;

    forming a semiconductor layer having a source area, a drain area and a channel area between the source area and the drain area by depositing a gate insulating layer and an oxide semiconductor material and patterning the oxide semiconductor material;

    forming an etch stopper on the semiconductor layer and the gate insulation layer to expose a portion of the source area and a portion of the drain area of the semiconductor layer;

    conducting a plasma treatment using the etch stopper as a mask to conductorize the portion of the source area and the portion of the drain area of the semiconductor layer exposed by the etch stopper for defining the channel area, the source area and the drain area; and

    forming a source electrode contacting the portion of the conductorized source area and a drain electrode contacting the portion of the conductorized drain area,wherein the forming the source electrode and the drain electrode includes;

    depositing a first metal layer and a second metal layer sequentially on the etch stopper;

    patterning the second metal layer with an wet etching method; and

    patterning the first metal layer with a dry etching method using the patterned second metal layer as a mask,wherein the source electrode contacts a surface of the portion of the source area that is apart from the channel area with a first predetermined distance,wherein the drain electrode contacts a surface of the portion of the drain area that is apart from the channel area with a second predetermined distance, andwherein the etch stopper includes a first portion disposed on a portion of the gate insulation layer and a portion of the source area at a position in which the first portion overlaps the gate electrode, a second portion disposed on the channel area at a position in which the second portion overlaps the gate electrode, and a third portion disposed on another portion of the gate insulation layer and a portion of the drain area at a position in which the third portion overlaps the gate electrode.

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