Dual gate FD-SOI transistor

• US 10,134,894 B2
• Filed: 12/30/2015
• Issued: 11/20/2018
• Est. Priority Date: 11/12/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Kumar, Anand, Agrawal, Ankit
• Primary Examiner(s): Spalla, David
• Application Number:
  US14/985,264
• Publication Number:
  US 20160111534A1
• Time in Patent Office: 1,056 Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

Claims

1. A device, comprising:

a silicon substrate;

a first doped well having a first conductivity type;

a second doped well having the first conductivity type, the second doped well being physically separated from the first doped well;

a first pass gate formed on the silicon substrate, the first pass gate including a fully-depleted silicon-on-insulator (FD-SOI) dual gate NMOS transistor having;

a source terminal,

a drain terminal,

a primary gate,

a secondary gate in the first doped well, the primary gate having a first surface that is spaced apart from the secondary gate by a first distance, and

a secondary gate contact on the secondary gate, the secondary gate electrically coupled to the primary gate through the secondary gate contact, the secondary gate contact oriented in a direction transverse to the primary gate and extending from the secondary gate to a second surface, the second surface being spaced apart from the secondary gate by a second distance that is less than the first distance, each of the first voltage, the second voltage, and the third voltage being different from one another; and

a second pass gate formed on the silicon substrate, the second pass gate including a FD-SOI dual gate PMOS transistor having;

a source terminal,

a drain terminal,

a primary gate,

a secondary gate in the second doped well, and

a secondary gate contact on the secondary gate, the secondary gate electrically coupled to the primary gate through the secondary gate contact, the secondary gate contact oriented in a direction transverse to the primary gate.

2. The device of claim 1 wherein an input is coupled to the primary gates and to the secondary gates of each of the NMOS transistor and the PMOS transistor, and an output is coupled to one of the source terminal and the drain terminal.

3. The device of claim 1 wherein the primary and secondary gates of each of the NMOS transistor and the PMOS transistor are accessible from a front side of the silicon substrate.

4. The device of claim 1 wherein the drain terminals of each of the NMOS transistor and the PMOS transistor are electrically coupled to one another.

5. The device of claim 1 wherein the first and second doped wells comprise first and second N-wells, respectively.

6. A device, comprising:

a silicon substrate;

a first n-well in the substrate;

a second n-well in the substrate, the second n-well physically separate from the first n-well;

a buried oxide layer on the first and second n-wells;

a NMOS dual gate transistor having;

a source terminal configured to be electrically coupled to a first voltage,

a drain terminal,

a primary gate configured to be electrically coupled to a second voltage,

a secondary gate in the first n-well, and

a secondary gate contact on the secondary gate, the secondary gate electrically coupled to the primary gate and to the second voltage through the secondary gate contact, the primary and secondary gates being accessible from a front side of the silicon substrate, the first voltage and the second voltage being different from one another; and

a PMOS dual gate transistor having;

a source terminal configured to be electrically coupled to a third voltage that is different from the first voltage and the second voltage,

a drain terminal,

a primary gate configured to be electrically coupled to the second voltage,

a secondary gate in the second n-well, and

a secondary gate contact on the secondary gate, the secondary gate electrically coupled to the primary gate and to the second voltage through the secondary gate contact, the primary and secondary gates being accessible from a front side of the silicon substrate.

7. The device of claim 6 wherein the secondary gate contacts of the PMOS and NMOS transistors are oriented in a direction transverse to the respective primary gates.

8. The device of claim 6 wherein the drain terminals of the PMOS and NMOS transistors are electrically coupled to one another.

9. The device of claim 8 wherein the first voltage is an electrical ground voltage.

10. The device of claim 9 wherein the second voltage is an input voltage, and the drain terminals of the PMOS and NMOS transistors provide an output voltage based on the input voltage.

11. A device, comprising:

a silicon-on-insulator substrate including a buried oxide layer over a first doped region and a second doped region, the first and second doped regions having a same conductivity type and being physically separate from one another;

a NMOS dual gate transistor including;

a source region on the buried oxide layer;

a drain region on the buried oxide layer;

a channel region on the buried oxide layer and positioned between the source region and the drain region;

a primary gate overlying the channel region;

a secondary gate in the first doped region; and

a secondary gate contact on the first doped region and in abutting contact with the buried oxide layer, the secondary gate contact being electrically coupled to the primary gate and the secondary gate; and

a PMOS dual gate transistor including;

a source region on the buried oxide layer;

a drain region on the buried oxide layer;

a channel region on the buried oxide layer and positioned between the source region and the drain region;

a primary gate overlying the channel region;

a secondary gate in the second doped region; and

a secondary gate contact on the second doped region and in abutting contact with the buried oxide layer, the secondary gate contact being electrically coupled to the primary gate and the secondary gate.

12. The device of claim 11 wherein the first doped region, the second doped region, the source region of the NMOS dual gate transistor, and the drain region of the NMOS dual gate transistor have the same conductivity type.

13. The device of claim 11 wherein the first doped region is a first N-well, and the second doped region is a second N-well.

14. The device of claim 11, further comprising a first gate oxide between the channel region and the primary gate of the NMOS dual gate transistor, and a second gate oxide between the channel region and the primary gate of the PMOS dual gate transistor, wherein the buried oxide layer has a thickness at least ten times larger than a thickness of each of the first and second gate oxides.

15. The device of claim 11 wherein the buried oxide layer has a thickness in the range of 15-30 nm.

16. The device of claim 11 wherein the primary gates of the NMOS and PMOS dual gate transistors are metal gates.

17. The device of claim 11 wherein the primary gates of the NMOS and PMOS dual gate transistors include polysilicon.

18. The device of claim 11 wherein the source region, the drain region, and the channel region of each of the NMOS and PMOS dual gate transistors have a thickness in the range of 10-50 nm.

19. The device of claim 11, further comprising a gate oxide between the channel region and the primary gate of one of the NMOS and PMOS dual gate transistors, the gate oxide having a thickness of about 10 nm.

20. The device of claim 11, further comprising a gate oxide between the channel region and the primary gate of one of the NMOS and PMOS dual gate transistors, the gate oxide including at least one of silicon dioxide and hafnium oxide.