Semiconductor device including wrap around contact, and method of forming the semiconductor device

• US 10,134,905 B2
• Filed: 06/30/2016
• Issued: 11/20/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Guillorn, Michael A., Loubet, Nicolas Jean
• Primary Examiner(s): Ghyka, Alexander
• Application Number:
  US15/199,334
• Publication Number:
  US 20180006159A1
• Time in Patent Office: 873 Days
• Field of Search: None
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76889 by forming silicides of refractory metals
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of forming a wrap around contact, includes forming a plurality of semiconductor layers on a plurality of fin structures, forming a sacrificial gate on the plurality of semiconductor layers, forming an epitaxial layer on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers, forming a gate structure by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer, and forming a wrap around contact on the epitaxial layer.

Claims

1. A method of forming a wrap around contact, comprising:

forming a plurality of semiconductor layers on a plurality of fin structures;

forming a shallow trench isolation (STI) region between the plurality of fin structures, an upper surface of the STI region being coplanar with an upper surface of the plurality of fin structures;

forming a sacrificial gate on the plurality of semiconductor layers;

forming an epitaxial layer on the upper surface of the plurality of fin structures and on a sidewall of the plurality of semiconductor layers;

forming a gate structure by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer; and

forming a wrap around contact including a metal silicide layer on a surface of the epitaxial layer.

2. The method of claim 1, wherein the STI region comprises a plurality of shallow trench isolation (STI) regions formed between the plurality of fin structures, the wrap around contact being formed on the STI regions.

3. The method of claim 1, wherein the forming of the gate structure comprises forming a plurality of gate structures.

4. The method of claim 3, wherein the gate structure comprises a spacer formed on a side of the metal layer, and the forming of the wrap around contact comprises forming the wrap around contact on the spacer and on the epitaxial layer between the plurality of gate structures.

8. The method of claim 1, wherein the forming of the epitaxial layer comprises forming a conformal highly-doped epitaxial film.

11. The method of claim 1, further comprising:

forming a plurality of other semiconductor layers alternately with the plurality of semiconductor layers.

12. The method of claim 11, wherein the replacing of the semiconductor layers comprises:

performing an etching to remove the sacrificial gate and remove the semiconductor layers from between the other semiconductor layers.

5. A method of forming a wrap around contact, comprising:

forming a plurality of semiconductor layers on a plurality of fin structures;

forming a sacrificial gate on the plurality of semiconductor layers;

forming an epitaxial layer on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers;

forming a gate structure by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer; and

forming a wrap around contact on the epitaxial layer;

wherein the forming of the wrap around contact comprises;

forming a conformal metal liner layer; and

forming a barrier layer on the metal liner layer.

6. The method of claim 5, wherein the forming of the wrap around contact comprises:

annealing the metal liner layer to form the metal silicide layer, the wrap around contact comprising the metal silicide layer and the barrier layer.

7. The method of claim 6, further comprising:

forming a metal fill layer on the barrier layer.

9. A method of forming a wrap around contact, comprising:

forming a plurality of semiconductor layers on a plurality of fin structures;

forming a sacrificial gate on the plurality of semiconductor layers;

forming an epitaxial layer on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers;

forming a gate structure by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer;

forming a wrap around contact on the epitaxial layer;

forming a sacrificial layer to on the epitaxial layer;

forming a liner layer on the sacrificial layer;

forming an oxide layer on the liner layer; and

polishing the oxide layer.

10. The method of claim 9, wherein the sacrificial layer comprises germanium, the liner layer comprises silicon nitride and the oxide layer comprises titania-silica oxide.

13. A method of forming a wrap around contact, comprising:

forming a plurality of semiconductor layers on a plurality of fin structures;

forming a shallow trench isolation (STI) region between the plurality of fin structures, an upper surface of the STI region being coplanar with an upper surface of the plurality of fin structures;

forming a sacrificial gate on the plurality of semiconductor layers;

forming a faceted epitaxial layer on the upper surface of the plurality of fin structures and on a sidewall of the plurality of semiconductor layers;

forming a gate structure by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer; and

forming a wrap around contact including a metal silicide layer on a surface of the faceted epitaxial layer.

14. The method of claim 13, wherein the STI region comprises a plurality of shallow trench isolation (STI) regions between the plurality of fin structures, the wrap around contact being formed on the STI regions.

15. The method of claim 13, wherein the forming of the gate structure comprises forming a plurality of gate structures,

wherein the gate structure comprises a spacer formed on a side of the metal layer, and

wherein the forming of the wrap around contact comprises forming the wrap around contact on the spacer and on the faceted epitaxial layer between the plurality of gate structures.

16. The method of claim 13, wherein the forming of the wrap around contact comprises:

forming a conformal metal liner layer;

forming a barrier layer on the metal liner layer; and

annealing the metal liner layer to form the metal silicide layer, the wrap around contact comprising the metal silicide layer and the barrier layer.

17. The method of claim 16, further comprising:

forming a metal fill layer on the barrier layer.

18. The method of claim 13, wherein the forming of the faceted epitaxial layer comprises forming a conformal highly-doped faceted epitaxial film.

19. The method of claim 13, further comprising:

forming a sacrificial layer on the faceted epitaxial layer;

forming a liner layer on the sacrificial layer;

forming an oxide layer on the liner layer; and

polishing the oxide layer.

20. The method of claim 19, wherein the sacrificial layer comprises germanium, the liner layer comprises silicon nitride and the oxide layer comprises titania-silica oxide.

21. The method of claim 13, further comprising:

forming a plurality of other semiconductor layers alternately with the plurality of semiconductor layers.

22. The method of claim 21, wherein the replacing of the semiconductor layers comprises:

performing an etching to remove the sacrificial gate and remove the semiconductor layers from between the other semiconductor layers.

23. A method of forming a wrap around contact, comprising:

forming a plurality of shallow trench isolation (STI) regions between a plurality of fin structures;

alternately forming a plurality of semiconductor layers and a plurality of other semiconductor layers on the plurality of fin structures;

forming a plurality of sacrificial gates on the plurality of semiconductor layers and the plurality of other semiconductor layers;

forming an conformal highly-doped epitaxial layer on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers and a sidewall of the plurality of other semiconductor layers;

forming a plurality of gate structures by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer, the gate structure comprising a spacer formed on a side of the metal layer, the replacing of the semiconductor layers comprising performing an etching to remove the sacrificial gate and remove the semiconductor layers from between the other semiconductor layers; and

forming a wrap around contact on the epitaxial layer, the wrap around contact being formed on the STI regions, on the spacer and on the epitaxial layer between the plurality of gate structures, the forming of the wrap around contact comprising;

forming a conformal metal liner layer;

forming a barrier layer on the metal liner layer; and

annealing the metal liner layer to form a metal silicide.