Remote memory access functionality in a cluster of data processing nodes

• US 10,135,731 B2
• Filed: 02/12/2016
• Issued: 11/20/2018
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: III Holdings 2, LLC (Intellectual Ventures LLC)
• Original Assignee: III Holdings 2, LLC (Intellectual Ventures LLC)
• Inventors: Davis, Mark Bradley, Evans, Barry Ross, Borland, David James
• Primary Examiner(s): Khirodhar, Maharishi V
• Assistant Examiner(s): Hunt, Kenneth P
• Application Number:
  US15/042,489
• Publication Number:
  US 20160239415A1
• Time in Patent Office: 1,012 Days
• Field of Search: 709213-217, 709219, 710 22, 710 26, 711147, 711148, 711153
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 45/74 Address processing for routing
• CPC Class Codes: H04L 45/74591 using content-addressable memories [CAM]
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/253 using establishment or release of connections between ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/351 : for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/356 : for storage area networks
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02B 70/30 : Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/00 : Reducing energy consumption in communication networks

Abstract

A server apparatus comprises a plurality of server on a chip (SoC) nodes interconnected to each other through a node interconnect fabric. Each one of the SoC nodes has respective memory resources integral therewith. Each one of the SoC nodes has information computing resources accessible by one or more data processing systems. Each one of the SoC nodes configured with memory access functionality enabling allocation of at least a portion of said memory resources thereof to one or more other ones of the SoC nodes and enabling allocation of at least a portion of said memory resources of one or more other ones of the SoC nodes thereto based on a workload thereof.

Claims

1. A server card system, the system comprising:

a first server card including a device driver, wherein the first server card is configured to provide computing resources information to one or more data processing systems; and

a second server card including a memory controller comprising a direct memory access (DMA) engine, wherein the second server card is configured to allocate memory resources to one or more nodes of the first server card, and wherein the second server card is configured to allocate a first portion of the memory resources to a first one of the nodes of the first server card as a private memory resource,

wherein the device driver of the first server card is configured to initiate a read of the first portion of the memory resources, wherein the DMA engine is configured to generate an interrupt, and wherein the DMA engine is configured to transmit the interrupt to the first server card.

2. The system of claim 1, wherein the second server card is further configured to allocate a second portion of the memory resources to a plurality of the nodes of the first server card as a shared memory resource.

3. The system of claim 1, wherein the second server card is further configured to assess a workload of a particular one of the nodes of the first server card.

4. The system of claim 3, wherein the second server card is further configured to allocate an amount of the memory resources of the second server card based on the workload.

5. The system of claim 1, wherein:

the memory resources of the second server card are accessible by each one of a plurality of server nodes of the second server card; and

each one of the plurality of nodes of the second server card are configured to access a second portion of the memory resources of the second server node card and selectively allocate the second portion of the memory resources to one or more of the nodes of the first server card.

6. The system of claim 1, wherein:

the nodes of the first server card are each configured for inter-node communication via a node interconnect fabric established therebetween; and

the memory resources of the second server card are allocated to the nodes of the first server card via the node interconnect fabric.

7. The system of claim 6, wherein the second server card is further configured to:

assess a workload of a particular one of the nodes of the first server card; and

allocate an amount of the memory resources of the second server card based on the workload.

15. The system of claim 1, wherein the memory controller is a remote serial advanced technology attachment (SATA) controller, and wherein the device driver is configured to initiating the read by writing control registers in the remote SATA controller.

8. A data processing facility, comprising:

a server rack having a mounting structure configured to individually receive a plurality of server rack chassis;

a first server rack chassis engaged with the mounting structure of the server rack, wherein the first server rack chassis includes a first plurality of server nodes, each one of the plurality of server nodes comprises a device driver, wherein the first plurality of server nodes are configured to provide computing resources information to one or more data processing systems; and

a second server rack chassis engaged with the mounting structure of the server rack, wherein the second server rack chassis includes a second plurality of server nodes interconnected to the first plurality of server nodes through a node interconnect fabric, wherein each one of the second plurality of server nodes comprises a memory controller including a direct memory access (DMA) engine, wherein each one of the second plurality of server nodes is configured to allocate memory resources, and wherein a first portion of the memory resources is configured to be allocated to a first one of the first plurality of server nodes of the first server rack chassis as a private memory resources;

wherein the device driver of the first server card is configured to initiate a read of the first portion of the memory resources, wherein the DMA engine is configured to generate an interrupt, and wherein the DMA engine is configured to transmit the interrupt to the first server card.

9. The data processing facility of claim 8, wherein a second portion of the memory resources is configured to be allocated to a plurality of the first plurality of server nodes of the first server rack chassis as a shared memory resource.

10. The data processing facility of claim 9, wherein one of the second plurality of server nodes is further configured to:

assess a workload of a particular one of the first plurality of server nodes of the first server rack chassis; and

allocate an amount of the memory resources of the second server rack chassis based on the workload.

11. The data processing facility of claim 9, wherein:

the memory resources of the second server rack chassis are accessible by each one of the second plurality of server nodes; and

each one of the second plurality of server nodes of the second server rack chassis are configured to access a third portion of the memory resources and selectively allocate the third portion of the memory resources to one or more of the first plurality of server nodes of the first server rack chassis.

12. The data processing facility of claim 8, wherein the memory resources are allocated via the node interconnect fabric.

13. The data processing facility of claim 12, wherein one of the second plurality of server nodes is further configured to assess a workload of a particular one of the first plurality of server nodes of the first server rack chassis.

14. The data processing facility of claim 13, wherein one of the second plurality of server nodes is further configured to allocate an amount of the memory resources of the second server rack chassis based on the workload.

16. The data processing facility of claim 8, wherein the memory controller is a remote serial advanced technology attachment (SATA) controller, and wherein the device driver is configured to initiating the read by writing control registers in the remote SATA controller.