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Network-based computational accelerator

  • US 10,135,739 B2
  • Filed: 05/04/2016
  • Issued: 11/20/2018
  • Est. Priority Date: 05/07/2015
  • Status: Active Grant
First Claim
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1. A data processing device, comprising:

  • a first packet communication interface for communication with at least one host processor via a network interface controller (NIC);

    a second packet communication interface for communication with a packet data network;

    a memory, configured to hold a flow state table containing context information with respect to multiple packet flows conveyed between the host processor and the network via the first and second packet communication interfaces; and

    acceleration logic, which is coupled between the first and second packet communication interfaces and is configured to perform computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table,wherein the acceleration logic is configured, upon receiving in a given flow, through the second packet communication interface, a packet that is out of order, to mark the given flow as an out-of-order flow in the flow state table and to convey the packet through the first packet communication interface along with a notification that the given flow is out of order, andwherein the acceleration logic is configured, after conveying the notification that the given flow is out of order, to receive from the at least one host processor an update to the flow state table with respect to the given flow, and following the update, to resume performing the computational operations on the packets in the given flow.

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