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Self-authenticating chips

  • US 10,135,814 B2
  • Filed: 12/16/2016
  • Issued: 11/20/2018
  • Est. Priority Date: 04/09/2014
  • Status: Active Grant
First Claim
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1. A self-authenticating integrated circuit chip comprising:

  • one or more memory circuits on the integrated circuit, the one or more memory circuits providing a first memory region storing a first authentication code;

    a second memory region storing a second authentication code;

    a comparator circuit on the integrated circuit interconnected to at least said second memory region for providing an indicator of whether a given input to said comparator circuit matches said second authentication code stored in said second memory region;

    wherein said second authentication code within said second memory region cannot be extracted or modified by said integrated circuit or a chip reader and may only be accessed by said comparator to compare the given input to said comparator to said second authentication code; and

    an authentication circuit on the integrated circuit interconnected to said comparator and at least one of said one or more memory circuits wherein said authentication circuit is operable to;

    read said first authentication code from said first memory region;

    present said first authentication code to said comparator; and

    in response to receiving an indicator from said comparator indicating that said first authentication code matches said second authentication codeunlock a communication interface of said chip to allow data to be transmitted therethrough to a chip reader or unlock a third memory region of the integrated circuit.

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