Massive multi-dimensionality failure analytics with smart converged bounds

• US 10,139,446 B2
• Filed: 08/28/2015
• Issued: 11/27/2018
• Est. Priority Date: 08/28/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Joshi, Rajiv Vasant, Acar, Emrah
• Primary Examiner(s): Desta, Elias
• Application Number:
  US14/839,740
• Publication Number:
  US 20170059649A1
• Time in Patent Office: 1,187 Days
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

A method and a system including a processor performing a failure region exploration through uniform sampling of plurality of variables related to a circuit, the processor shifting probability distributions to explore failure probability, the processor estimating the failure probability and standard deviation by determining mean and standard deviation of failure probability of a circuit, the processor terminating sampling when a confidence interval bounds converge, and a peripheral device providing a report on the failure of the circuit when the sampling is terminated by the processor.

Claims

1. A computer system executing a method stored in a computer readable medium, comprising:

a processor performing a failure region exploration through uniform sampling of plurality of variables related to a circuit;

the processor estimating a failure probability and standard deviation by determining mean and standard deviation of failure probability of a circuit;

the processor terminating sampling when a confidence interval bounds converge; and

a peripheral device providing a report on the failure of the circuit when the sampling is terminated by the processor.

2. The computer system according to claim 1, wherein the confidence interval bounds include an upper bound sigma estimate, a lower bound sigma estimate, and sigma estimate, and

wherein the processor stops sampling when the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate substantially converge.

3. The computer system according to claim 2, wherein the processor stops sampling when the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate converge by a predetermined threshold and before divergence of the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate.

4. The computer system according to claim 1, wherein the confidence interval bounds include an upper bound sigma estimate, a lower bound sigma estimate, and sigma estimate, and

wherein the processor stops sampling when the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate substantially converge by a predetermined threshold.

5. The computer system according to claim 1, wherein the variance of the probability of the failure is calculated based on the sample weights of an applied mixed importance sampling.

6. The computer system according to claim 1, further comprising the processor shifting probability distributions from the failure region exploration to explore failure probability,

wherein the probability of failure and the statistical variance are evaluated incrementally for each variable.

7. The computer system according to claim 1, wherein the processor prunes the number of variables through with known statistical variations based on the probability of failure and statistical variance calculated within a simulation of the circuit.

15. The system according to claim 1, wherein the probability of failure and the statistical variance are evaluated incrementally for each variable.

16. The system according to claim 1, wherein the processor prunes the number of variables through with known statistical variations based on the probability of failure and statistical variance calculated within the simulations of the circuit.

8. A system for computing and modeling the probability of a failure of a circuit, comprising:

a processor measuring a system functionality by an indicator function based on one or more output variables and pre-given. thresholds stored in a computer readable medium;

the processor simulating a system behavior for a sequence of samples of random model parameters; and

the processor determining the probability of failure and the statistical variance of that are being evaluated at each sampling stage.

9. The system according to claim 8, further comprising the processor terminating a sequence of the simulations when the said statistical variance is below a predetermined target, and a rate of change of the variance is below a threshold designed as a stopping criterion,

wherein the system exhibits inherent variability with a multitude of model parameters under prescribed statistical variability.

10. The system according to claim 8, wherein the termination of the sequence of simulation when convergence is made between an upper bound, lower bound and a sigma estimate.

11. The system according to claim 8, further comprising the processor pruning key variables which are input for the plurality of simulations.

12. The system according to claim 8, wherein the processor determines an upper bound sigma estimate, a lower bound sigma estimate, and sigma estimate, and

wherein the processor stops sampling when the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate substantially converge by the predetermined threshold.

13. The system according to claim 12, wherein the processor stops sampling when the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate converge by a predetermined threshold and before divergence of the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate.

14. The system according to claim 8, wherein the variance of the probability of the failure is calculated based on the sample weights of an applied mixed importance sampling.

17. A method computing and modeling the probability of a failure of a device, the method comprising:

performing a failure region exploration through uniform sampling of plurality of variables related to the device;

estimating a failure probability and standard deviation by determining mean and standard deviation of failure probability of a device;

terminating sampling when a confidence interval bounds converge; and

providing a report on the failure of the circuit when the sampling is terminated.

18. The method according to claim 17, further comprising the shifting probability distributions from the failure region exploration to explore failure probability,

wherein the confidence interval bounds include an upper bound sigma estimate, a lower bound sigma estimate, and sigma estimate, and

wherein a processor stops sampling when the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate substantially converge.

19. The method according to claim 18, wherein the processor stops sampling when the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate converge by a predetermined threshold and before divergence of the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate.

20. The method according to claim 17, wherein the confidence interval bounds include an upper bound sigma estimate, a lower bound sigma estimate, and sigma estimate, and

wherein a processor stops sampling when the upper bound sigma estimate, the lower bound sigma estimate, and the sigma estimate substantially converge by a predetermined threshold.