Data bus driving circuit, and semiconductor device and semiconductor memory device including the same

• US 10,140,241 B2
• Filed: 07/17/2017
• Issued: 11/27/2018
• Est. Priority Date: 04/23/2014
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Takahashi, Hiroyuki
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US15/651,091
• Publication Number:
  US 20170315952A1
• Time in Patent Office: 498 Days
• Field of Search: 714758, 714760, 714762
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor device includes a data processing unit that processes input data and outputs processed data, a logic inversion unit that receives the processed data, inverts the processed data based on a determination result signal to be transmitted to a data bus, and an inversion determination unit that compares the input data which has not been processed by the data processing unit with the output data of the logic inversion unit corresponding to a preceding input data, and generates the determination result signal based on a comparison result.

Claims

1. A semiconductor device, comprising:

a data processing unit that processes input data and outputs processed data;

a logic inversion unit that receives the processed data, inverts the processed data based on a determination result signal to be transmitted to a data bus; and

an inversion determination unit that compares the input data which has not been processed by the data processing unit with the output data of the logic inversion unit corresponding to a preceding input data, and generates the determination result signal based on a comparison result.

2. The semiconductor device according to claim 1, wherein the logic inversion unit includes a first logic inversion unit and the semiconductor device further comprises a second logic inversion unit coupled to the first logic inversion unit through the data bus, and a logic unit,

wherein the second logic inversion unit inverts the data transmitted through the data bus based on the determination result signal, and

wherein the logic unit receives output data of the second logic inversion unit.

3. The semiconductor device according to claim 1, further comprising a memory cell array,

wherein the data processing unit comprises an Error Check and Correct (ECC) decoding unit that performs an error correction processing on the input data using a corresponding error correction code, and that outputs the corrected input data as the processed data, the input data and the corresponding error correction code being read out from the memory cell array.

4. The semiconductor device according to claim 1, wherein the logic inversion unit includes a first logic inversion unit and a second logic inversion unit, and the data bus includes a first data bus,

wherein the semiconductor device further comprises a second data bus and an Error Check and Correct (ECC) encoding unit that generates an error correction code based on the input data, and

wherein the second logic inversion unit inverts the error correction code based on the determination result signal to be transmitted to the second data bus.

5. The semiconductor device according to claim 4, further comprising a third logic inversion unit and a fourth logic inversion unit,

wherein the third logic inversion unit is coupled to the first logic inversion unit through the first data bus, the fourth logic inversion unit is coupled to the second logic inversion unit through the second data bus, and the third logic inversion unit and the fourth logic inversion unit invert the processed data and the error correction code based on the determination result signal, respectively.

6. The semiconductor device according to claim 5, further comprising a memory cell array,

wherein an output of the third logic inversion unit and an output of the fourth logic inversion unit are written into the memory cell array.

7. The semiconductor device according to claim 4, wherein bit numbers of the error correction code are smaller than bit numbers of the input data.