Array substrate and driving method thereof, display panel and display device

• US 10,140,903 B2
• Filed: 04/20/2015
• Issued: 11/27/2018
• Est. Priority Date: 11/28/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Lee, Chungchun, Duan, Liye, Li, Yanzhao, Wu, Chunwei, Park, Hanjun
• Primary Examiner(s): Shah, Priyank J
• Application Number:
  US14/785,709
• Publication Number:
  US 20160335937A1
• Time in Patent Office: 1,317 Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0804 Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2340/0457 Improvement of perceived resolution by subpixel rendering
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/2074 using sub-pixels
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

The invention provides an array substrate and a driving method thereof, a display panel and a display device. The array substrate comprises a plurality of circulating units and a plurality of pixel circuits. Each circulating unit consists of four sub-pixel units located in four columns and two rows, sub-pixel units in any two adjacent columns are located in different rows and have different colors, and sub-pixel units in at least one row have different colors. Each sub-pixel unit is connected to one pixel circuit, and each sub-pixel unit comprises a first sub-pixel and a second sub-pixel located in the same column and having the same color. The pixel circuit is configured to drive the first sub-pixel when a first frame picture is displayed, and to drive the second sub-pixel when a second frame picture is displayed.

Claims

1. An array substrate, comprising a plurality of circulating units and a plurality of pixel circuits, wherein

each circulating unit consists of four sub-pixel units located in four columns and two rows, sub-pixel units in any two adjacent columns are located in different rows and have different colors, and sub-pixel units in at least one row have different colors;

each sub-pixel unit comprises a first sub-pixel and a second sub-pixel located in the same column and having the same color, and both the first sub-pixel and the second sub-pixel are connected to a same pixel circuit; and

the pixel circuit is configured to drive the first sub-pixel when a first frame picture is displayed, and to drive the second sub-pixel when a second frame picture is displayed,

wherein each pixel circuit of the plurality of pixel circuits comprises a first sub-pixel circuit and a second sub-pixel circuit, the first sub-pixel circuit comprises a first driving transistor and the second sub-pixel circuit comprises a second driving transistor, the first sub-pixel circuit and the second sub-pixel circuit share a compensation unit, and are controlled by a same data line, which is connected to a control unit;

the compensation unit is configured to adjust a gate voltage of the first driving transistor in the first sub-pixel circuit to eliminate influence of a threshold voltage of the first driving transistor on a driving current of the first sub-pixel, and to adjust a gate voltage of the second driving transistor in the second sub-pixel circuit to eliminate influence of a threshold voltage of the second driving transistor on a driving current of the second sub-pixel;

the compensation unit comprises a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, a tenth switching transistor, a first storage capacitor and a second storage capacitor;

a gate of the first switching transistor and a gate of the seventh switching transistor are connected to a first light emitting control line, a source of the first switching transistor is connected to a source of the second switching transistor and a first reference voltage source, and a drain of the first switching transistor is connected to a source of the fourth switching transistor and a source of the first driving transistor;

a gate of the second switching transistor is connected to a gate of the eighth switching transistor and a second light emitting control line, and a drain of the second switching transistor is connected to a source of the fifth switching transistor and a source of the second switching transistor;

a gate of the third switching transistor is connected to a gate of the fourth switching transistor and a first scanning line, a source of the third switching transistor is connected to the data line, a drain of the third switching transistor is connected to a second terminal of the first storage capacitor and a source of the seventh switching transistor;

a drain of the fourth switching transistor is connected to a first terminal of first storage capacitor and a gate of the first driving transistor;

a gate of the fifth switching transistor is connected to a gate of the sixth switching transistor and a second scanning line, and a drain of the fifth switching transistor is connected to a first terminal of the second storage capacitor and a gate of the second driving transistor;

a source of the sixth switching transistor is connected to the data line, a drain of the sixth switching transistor is connected to a second terminal of the second storage capacitor and a source of the eighth switching transistor;

a drain of the seventh switching transistor is connected to a source of the ninth switching transistor, a drain of the first driving transistor and a first terminal of the first sub-pixel, and a second terminal of the first sub-pixel is grounded;

a drain of the eighth switching transistor is connected to a source of the tenth switching transistor, a drain of the second driving transistor and a first terminal of the second sub-pixel, and a second terminal of the second is sub-pixel is grounded;

a gate of the ninth switching transistor is connected to a gate of the tenth switching transistor and the second scanning line, and a drain of the ninth switching transistor is grounded; and

a drain of the tenth switching transistor is grounded.

2. The array substrate according to claim 1, wherein the circulating unit comprises one red sub-pixel unit, one blue sub-pixel unit and two green sub-pixel units.

3. The array substrate according to claim 1, wherein the circulating unit comprises one red sub-pixel unit, one green sub-pixel unit, one blue sub-pixel unit and one white sub-pixel unit.

4. The array substrate according to claim 1, wherein

the first sub-pixel circuit is connected to the first sub-pixel, and the second sub-pixel circuit is connected to the second sub-pixel;

and

the control unit is configured to control the first sub-pixel circuit to drive the first sub-pixel when the first frame picture is displayed, and to control the second sub-pixel circuit to drive the second sub-pixel when the second frame picture is displayed.

5. The array substrate according to claim 2, wherein

the first sub-pixel circuit is connected to the first sub-pixel, and the second sub-pixel circuit is connected to the second sub-pixel;

and

the control unit is configured to control the first sub-pixel circuit to drive the first sub-pixel when the first frame picture is displayed, and to control the second sub-pixel circuit to drive the second sub-pixel when the second frame picture is displayed.

6. The array substrate according to claim 3, wherein

the first sub-pixel circuit is connected to the first sub-pixel, and the second sub-pixel circuit is connected to the second sub-pixel;

and

the control unit is configured to control the first sub-pixel circuit to drive the first sub-pixel when the first frame picture is displayed, and to control the second sub-pixel circuit to drive the second sub-pixel when the second frame picture is displayed.

7. The array substrate according to claim 4, further comprising a plurality of data lines, and the first sub-pixel circuit and the second sub-pixel circuit in each pixel circuit are connected to the same data line.

8. The array substrate according to claim 5, further comprising a plurality of data lines, and the first sub-pixel circuit and the second sub-pixel circuit in each pixel circuit are connected to the same data line.

9. The array substrate according to claim 6, further comprising a plurality of data lines, and the first sub-pixel circuit and the second sub-pixel circuit in each pixel circuit are connected to the same data line.

10. A display panel, comprising the array substrate according to claim 1.

11. A display device, comprising the display panel according to claim 10.

12. A driving method of an array substrate, the array substrate comprising a plurality of circulating units and a plurality of pixel circuits, wherein

each circulating unit consists of four sub-pixel units located in four columns and two rows, sub-pixel units in any two adjacent columns are located in different rows and have different colors, and sub-pixel units in at least one row have different colors:

each sub-pixel unit comprises a first sub-pixel and a second sub-pixel located in the same column and having the same color, and both the first sub-pixel and the second sub-pixel are connected to a same pixel circuit; and

the pixel circuit is configured to drive the first sub-pixel when a first frame picture is displayed, and to drive the second sub-pixel when a second frame picture is displayed,

wherein each pixel circuit of the plurality of pixel circuits comprises a first sub-pixel circuit and a second sub-pixel circuit, the first sub-pixel circuit comprises a first driving transistor and the second sub-pixel circuit comprises a second driving transistor, the first sub- pixel circuit and the second sub-pixel circuit share a compensation unit, and are controlled by a same data line, which is connected to a control unit;

the compensation unit is configured to adjust a gate voltage of the first driving transistor in the first sub-pixel circuit to eliminate influence of a threshold voltage of the first driving transistor on a driving current of the first sub-pixel; and

to adjust a gate voltage of the second driving transistor in the second sub-pixel circuit to eliminate influence of a threshold voltage of the second driving transistor on a driving current of the second sub-pixel;

the compensation unit comprises a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, a tenth switching transistor, a first storage capacitor and a second storage capacitor;

a gate of the first switching transistor and a gate of the seventh switching transistor are connected to a first light emitting control line, a source of the first switching transistor is connected to a source of the second switching transistor and a first reference voltage source, and a drain of the first switching transistor is connected to a source of the fourth switching transistor and a source of the first driving transistor;

a gate of the second switching transistor is connected to a gate of the eighth switching transistor and a second light emitting control line, and a drain of the second switching transistor is connected to a source of the fifth switching transistor and a source of the second switching transistor;

a gate of the third switching transistor is connected to a gate of the fourth switching transistor and a first scanning line a source of the third switching transistor is connected to the data line, a drain of the third switching transistor is connected to a second terminal of the first storage capacitor and a source of the seventh switching transistor;

a drain of the fourth switching transistor is connected to a first terminal of the first storage capacitor and a gate of the first driving transistor;

a gate of the fifth switching transistor is connected to a gate of the sixth switching transistor and a second scanning line, and a drain of the fifth switching transistor is connected to a first terminal of the second storage capacitor and a gate of the second driving transistor;

a source of the sixth switching transistor is connected to the data line, a drain of the sixth switching transistor is connected to a second terminal of the second storage capacitor and a source of the eighth switching transistor;

a drain of the seventh switching transistor is connected to a source of the ninth switching transistor, a drain of the first driving transistor and a first terminal of the first sub-pixel, and a second terminal of the first sub-pixel is grounded;

a drain of the eighth switching transistor is connected to a source of the tenth switching transistor, a drain of the second driving transistor and a first terminal of the second sub-pixel, and a second terminal of the second sub-pixel is grounded;

a gate of the ninth switching transistor is connected to a gate of the tenth switching transistor and the second scanning line, and a drain of the ninth switching transistor is grounded; and

a drain of the tenth switching transistor is grounded,

the driving method comprising;

driving, by the pixel circuit, the first sub-pixel in the sub-pixel unit connected to the pixel circuit when a first frame picture is displayed; and

driving, by the pixel circuit, the second sub-pixel in the sub-pixel unit connected to the pixel circuit when a second frame picture is displayed.

13. The driving method according to claim 12, wherein the circulating unit comprises one red sub-pixel unit, one blue sub-pixel unit and two green sub-pixel units.

14. The driving method according to claim 12, wherein the circulating unit comprises one red sub-pixel unit, one green sub-pixel unit, one blue sub-pixel unit and one white sub-pixel unit.

15. The driving method according to claim 12, wherein

the first sub-pixel circuit is connected to the first sub-pixel, and the second sub-pixel circuit is connected to the second sub-pixel;

and

the control unit is configured to control the first sub-pixel circuit to drive the first sub-pixel when the first frame picture is displayed, and to control the second sub-pixel circuit to drive the second sub-pixel when the second frame picture is displayed.

16. The driving method according to claim 15, wherein the array substrate further comprises a plurality of data lines, and the first sub-pixel circuit and the second sub-pixel circuit in each pixel circuit are connected to the same data line.