Memory device comprising an electrically floating body transistor

• US 10,141,046 B2
• Filed: 12/19/2017
• Issued: 11/27/2018
• Est. Priority Date: 01/15/2014
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Widjaja, Yuniarto
• Primary Examiner(s): Bernstein, Allison P
• Application Number:
  US15/846,566
• Publication Number:
  US 20180122457A1
• Time in Patent Office: 343 Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 15/043 using capacitive charge storage elements
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

Claims

1. A memory cell comprising:

an electrically floating body region comprising a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a source line region comprising a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type, said source line region in physical contact with said electrically floating body region;

a drain region comprising said second conductivity type in physical contact with said electrically floating body region and spaced apart from said source line region;

a first charge injector region, wherein said first charge injector region comprises said second conductivity type and is in physical contact with said electrically floating body region and spaced apart from said source line region and said drain region;

a second charge injector region, wherein said second charge injector region comprises said second conductivity type and is in physical contact with said electrically floating body region and spaced apart from said source line region, said drain region, and said first charge injector region;

a gate positioned in between said source line region and said drain region, the same gate being positioned between said first charge injector region and said second charge injector region; and

wherein said electrically floating body region is configured to have more than one stable state through an application of a bias on said first and second charge injector regions.

2. The memory cell of claim 1 configured such that a holding operation on said memory cell does not require any interruption to access to said memory cell.

3. A memory array comprising a plurality of said memory cells of claim 1, arranged in at least one row and at least one column.

4. The array of claim 3, comprising a charge injector terminal connected to all of said memory cells in a row or column of said array;

wherein said charge injector terminal is configured to perform a holding operation on all of said memory cells connected to said charge injector terminal in a batch operation, so that no individual selection of one of said memory cells is required to perform the holding operation.

5. The memory cell of claim 1, wherein application of a charge to at least one of said first charge injector region or said second charge injector in performance of a holding operation also increases a size of a memory window of said floating body region.

6. The memory cell of claim 1, wherein depths of each of said first and second charge injector regions are less than a depth of said drain region or said source line region.

7. The memory cell of claim 1, wherein depths of each of said first and second charge injector regions are less than a depth of said floating body region.

8. A memory device comprising the memory cell of claim 1 connected in series to an access device.

9. The memory device of claim 8, wherein said access device comprises:

a body region comprising said first conductivity type;

a second source line region comprising said second conductivity type in contact with said body region;

a second drain region comprising said second conductivity type in contact with said body region and spaced apart from said second source line region; and

a body tap region comprising said first conductivity type in contact with said body region.

10. The memory device of claim 9, wherein said body tap region is configured to apply a bias on said body region.

11. The memory device of claim 8, wherein said memory cell and said access device comprise two transistors each having a same conductivity type.

12. The memory device of claim 8, wherein said memory cell and said access device comprise two transistors each having a different conductivity type.

13. A memory device comprising the memory cell of claim 1, connected in series to an access device;

wherein said access device comprises;

a body region comprising said first conductivity type;

a second source line region comprising said second conductivity type in contact with said body region; and

a second drain region comprising said second conductivity type in contact with said body region and spaced apart from said second source line region.

14. A content addressable memory cell comprising:

the memory cell of claim 1, wherein said electrically floating body region comprise a first electrical floating body region; and

a second electrically floating body region;

wherein said first electrically floating body region and said second electrically floating body region are electrically connected in series through a common node; and

wherein said first electrically floating body region and said second electrically floating body region store complementary data.

15. The memory cell of claim 1 fabricated in a silicon-on-insulator (SOI) substrate.

16. The memory cell of claim 1 fabricated in a bulk silicon substrate and further comprising a buried well region comprising said second conductivity type.