Page writes for triple level cell flash memory

• US 10,141,050 B1
• Filed: 04/27/2017
• Issued: 11/27/2018
• Est. Priority Date: 04/27/2017
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Pure Storage, Inc.
• Inventors: Kannan, Hari, Kirkpatrick, Peter E.
• Primary Examiner(s): Tran, Uyen B
• Application Number:
  US15/498,979
• Time in Patent Office: 579 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.

Claims

1. A method for page writes for triple level cell, or higher level cell, flash memory, comprising:

receiving data in a storage system, from a client that is agnostic of page write requirements for the triple level cell, or higher level cell, flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages;

accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple level cell, or higher level cell, flash memory in the storage system; and

writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or higher level cell, flash memory in the storage system as an atomic write, wherein the page write requirements for the triple level cell, or higher level cell, flash memory comprise writing a lower page, an upper page and an extra page to assure read coherency of cells, and the writing at least the portion of received data comprises writing the lower page, the upper page and the extra page as the atomic write.

2. The method of claim 1, further comprising:

supporting the atomic write with an energy reserve.

3. The method of claim 1, further comprising:

writing further data to a portion of flash memory in the storage system having page write requirements differing from the triple level cell, or higher level cell, flash memory.

4. The method of claim 1, wherein the client is one of a client that is external to the storage system, sending user data, or a client internal to the storage system, sending metadata or error coded user data.

5. The method of claim 1, further comprising:

writing an extra page from the RAM to the triple level cell, or higher level, cell flash memory in the storage system as a further atomic write, wherein the writing at least the portion of received data comprises writing a lower page and an upper page as the atomic write in accordance with the page write requirements comprising writing the lower page and the upper page to assure read coherency of cells.

6. The method of claim 1, further comprising:

writing at least one further page to a further portion of flash memory in the storage system as a further atomic write, wherein the triple level cell, or higher level cell, flash memory has a first page size and the further portion of flash memory has a second, differing page size.

7. A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising:

receiving data in a storage system, from a client that is uninvolved with page write requirements for triple level cell, or higher level cell, flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages;

gathering the received data into random access memory (RAM) in the storage system to satisfy the page write requirements of the triple level cell, or higher level cell, flash memory in the storage system;

sending at least a portion of the gathered data in accordance with the page write requirements of the triple level cell, or higher level cell, flash memory, from the RAM to a write sequencer in the storage system for writing as an atomic write to the triple level cell, or higher level cell, flash memory, and

sending an extra page from the RAM to the write sequencer as a further atomic write after the atomic write, wherein the page write requirements of the triple level cell, or higher level cell, flash memory comprise writing the lower page and the upper page prior to writing the extra page, to assure read coherency of cells in the triple level cell, or higher level cell, flash memory.

8. The computer-readable media of claim 7, wherein the method further comprises:

writing further data to a differing portion of flash memory in the storage system in accordance with page write requirements of a further portion of flash memory, wherein the differing portion of flash memory and the triple level cell, or the higher level cell, flash memory have differing page write requirements.

9. The computer-readable media of claim 7, wherein the receiving data in the storage system comprises one of receiving user data from a client external to the storage system or receiving metadata or error coded user data from one of a plurality of authorities in the storage system, each authority owning a range of user data.

10. The computer-readable media of claim 7, wherein the sending at least the portion of the gathered data to the write sequencer comprises sending a lower page, an upper page and an extra page as the atomic write, wherein the page write requirements for the triple level cell, or higher level cell, flash memory comprise writing the lower page, the upper page and the extra page to assure read coherency of cells in the triple level cell, or higher level cell, flash memory.

11. The computer-readable media of claim 7, wherein the method further comprises:

writing at least one further page to a further portion of flash memory in the storage system as a further atomic write in accordance with page write requirements of a further portion of flash memory, wherein the triple level cell, or the higher level cell, flash memory and the further portion of flash memory have differing page sizes.

12. A storage system, comprising:

a plurality of portions of flash memory, including a portion of triple level cell, or higher level cell, flash memory;

a write sequencer, configurable to write pages to the plurality of portions of flash memory, the write sequencer having a plurality of channels each configurable as to page write requirements, with the portion of the triple level cell, or the higher level cell, flash memory coupled to a first channel and a further portion of flash memory having a differing page write requirement coupled to a second channel;

at least one processor, configurable to receive data from a client that is isolated from page write requirements for flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages; and

the at least one processor further configurable to accrue data to satisfy the page write requirements of the triple level cell, or higher level cell, flash memory and send at least a portion of the accrued data to the write sequencer for writing in accordance with the page write requirements to the portion of triple level cell, or higher level cell, flash memory as an atomic write.

13. The storage system of claim 12, further comprising:

an energy reserve coupled to the write sequencer and coupled to random access memory (RAM) as nonvolatile random access memory (NVRAM), the energy reserve having sufficient energy capacity to support the atomic write from the NVRAM to the portion of triple level cell, or higher level cell, flash memory in case of power failure.

14. The storage system of claim 12, further comprising:

a plurality of blades, having a plurality of storage nodes coupled together as a storage cluster and having a plurality of authorities within and transferable among the storage nodes, at least one of the plurality of storage nodes having two of the plurality of authorities, wherein the at least one processor configurable to receive data from a client comprises the at least one processor in a one of the plurality of storage nodes and configurable to receive metadata or error coded user data from one of the plurality of authorities.

15. The storage system of claim 12, wherein the at least one processor configured to accrue and to send comprises:

the at least one processor configured to accrue a lower page and an upper page and to send the lower page and the upper page to the write sequencer as the atomic write, wherein the page write requirements are of triple level cell flash memory and comprise writing the lower page and the upper page to assure read coherency of cells in the triple level cell flash memory.

16. The storage system of claim 12, wherein the at least one processor configured to accrue and to send comprises:

the at least one processor configured to accrue a lower page, an upper page and an extra page and to send the lower page, the upper page and the extra page to the write sequencer as the atomic write, wherein the page write requirements are of triple level cell flash memory and comprise writing the lower page, the upper page and the extra page to assure read coherency of cells in the triple level cell flash memory.

17. The storage system of claim 12, wherein the write sequencer configurable to write pages comprises:

the write sequencer, configurable to write pages to the plurality of portions of flash memory in accordance with differing page write requirements and differing page sizes of differing portions of flash memory.