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Memory device architecture

  • US 10,141,051 B2
  • Filed: 08/14/2017
  • Issued: 11/27/2018
  • Est. Priority Date: 10/12/2012
  • Status: Active Grant
First Claim
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1. A system, comprising:

  • a memory device comprising;

    an array of memory cells occupying a footprint; and

    a plurality of word line drivers and digit line drivers in a circuit level positioned below the array of memory cells, wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points distributed within the footprint.

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