Multi-chip non-volatile semiconductor memory package including heater and sensor elements

• US 10,141,058 B1
• Filed: 03/05/2015
• Issued: 11/27/2018
• Est. Priority Date: 02/17/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Darryl G. Walker
• Inventors: Walker, Darryl G.
• Primary Examiner(s): Tran, Anthan
• Assistant Examiner(s): Siddique, Mushfique
• Application Number:
  US14/639,301
• Time in Patent Office: 1,363 Days
• Field of Search: 36518509
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 22/10 Measuring as part of the manufacturing process burn-in G01R31/2855
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H05B 3/146 : Conductive polymers, e.g. polyethylene, thermoplastics
• CPC Class Codes: H05B 3/148 : Silicon, e.g. silicon carbide, magnesium silicide, heating transistors or diodes
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a temperature range having a temperature range upper limit value and a temperature range lower limit value. The temperature of the multi-chip package can be kept essentially within the temperature range for a predetermined time period by monitoring a thermal sensing element with a sensing circuit outside of the multi-chip package. The thermal sensing element may be located near the components with the lowest failure temperature to ensure the multi-chip package is not damaged during the healing process.

Claims

1. A non-volatile memory system, comprising:

a chip package, the chip package comprising

a first non-volatile semiconductor memory device;

a heater element that provides heat to the first non-volatile semiconductor memory device; and

a thermal sensing element, the thermal sensing element has a parameter that changes in response to changes in temperature; and

a heat control circuit coupled to provide a heat drive signal;

wherein

the heater element includes a first terminal coupled to receive the heat drive signal, and

the heat control circuit is coupled to receive a heat enable signal and a temperature range lower limit detect signal, the heat control circuit provides a low impedance path between a power supply potential and the first terminal of the heater element in response to the heat enable signal being in an enable logic level and the temperature range lower limit detect signal indicating the temperature of the thermal sensing element is below a temperature range lower value.

2. The non-volatile memory system of claim 1, wherein:

the first non-volatile semiconductor memory device is sandwiched between the heater element and the thermal sensing element.

3. The non-volatile memory system of claim 2, wherein:

the chip package further includes solder connections disposed on a bottom surface wherein the thermal sensing element is between the solder connections and the first non-volatile semiconductor memory device.

4. The non-volatile memory system of claim 3, wherein:

the thermal sensing element is formed on a substrate, the substrate includes a plurality of first vias forming electrical connections through the substrate and between the solder connections and the first non-volatile semiconductor memory device.

5. The non-volatile memory system of claim 4, further including:

the thermal sensing element is formed between the plurality of first vias.

6. The non-volatile memory system of claim 1, wherein:

the heat control circuit is coupled to receive a temperature range upper limit detect signal, the heat control circuit provides a high impedance path between a power supply potential and the first terminal of the heater element in response to the heat enable signal being in the enable logic level and the temperature range upper limit detect signal indicating the temperature of the thermal sensing element is above a temperature range upper value.

7. The non-volatile memory system of claim 1, wherein:

the heat control circuit is coupled to receive the temperature range lower limit detect signal and a temperature range upper limit detect signal wherein the heat control circuit provides the heat drive signal in response to logic states of the temperature range lower limit detect signal and the temperature range upper limit detect signal.

8. The non-volatile memory system of claim 1, further including:

the heat control circuit is outside the chip package.

9. The non-volatile memory system of claim 1, wherein:

the chip package further includes

a second non-volatile semiconductor memory device and the first and second non-volatile semiconductor memory devices are sandwiched between the heater element and the thermal sensing element.

10. The non-volatile memory system of claim 1, wherein:

the heater element and the thermal sensing element are formed on a substrate; and

the substrate is above a top surface of the first non-volatile semiconductor memory device.

11. The non-volatile memory system of claim 1, wherein:

the chip package further includes

a second non-volatile semiconductor memory device and the heater element and thermal sensing element are sandwiched between the first non-volatile semiconductor memory device and the second non-volatile semiconductor memory device.

12. The non-volatile memory system of claim 1, wherein:

the chip package further includes

a second non-volatile semiconductor memory device and the heater element is sandwiched between the first non-volatile semiconductor memory device and the second non-volatile semiconductor memory device.

13. The non-volatile memory system of claim 1, further including:

the chip package further includes a plurality of solder connections disposed on a bottom surface; and

the heater element includes a first terminal electrically connected to one of the plurality of solder connections.

14. The non-volatile memory system of claim 1, further including:

the chip package further includes a plurality of solder connections disposed on a bottom surface;

the thermal sensing element includes a first terminal and second terminal; and

the first terminal electrically connected to a first one of the plurality of solder connections and the second terminal is electrically connected to a second one of the plurality of solder connections.

15. A non-volatile memory system, comprising:

a chip package, the chip package comprising

a first non-volatile semiconductor memory device;

a heater element that provides heat to the first non-volatile semiconductor memory device; and

a thermal sensing element, the thermal sensing element has a parameter that changes in response to changes in temperature;

wherein

the thermal sensing element has a first terminal coupled to a first sense node and a second terminal coupled to a second sense node; and

a sensor circuit coupled to receive the first and second sense nodes and provide a temperature range upper limit detect signal in response to the value of the parameter of the thermal sensing element.

16. The non-volatile memory system of claim 15, further including:

the sensor circuit provides a temperature range lower limit detect signal in response to the value of the parameter of the thermal sensing element.

17. The non-volatile memory system of claim 15, further including:

the sensor circuit is outside the chip package.