Fabricating method of a semiconductor device with a high-K dielectric layer having a U-shape profile

• US 10,141,193 B2
• Filed: 11/24/2015
• Issued: 11/27/2018
• Est. Priority Date: 06/16/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chien, Chin-Cheng, Wu, Chun-Yuan, Liu, Chih-Chien, Lin, Chin-Fu, Tsai, Teng-Chun
• Primary Examiner(s): Pizarro, Marcos D
• Application Number:
  US14/949,896
• Publication Number:
  US 20160079067A1
• Time in Patent Office: 1,099 Days
• Field of Search: 438591, 438592, 438596
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.

Claims

1. A fabricating method of a semiconductor device, comprising:

forming an inter layer dielectric layer on a substrate;

forming a trench in the inter layer dielectric layer;

forming a high-k dielectric layer having a U-shape profile in the trench;

transforming two ends of the U-shape profile to a metal layer, wherein the transforming step is a reduction;

after transforming the two ends of the U-shape profile to the metal layer, forming a work function metal layer on the high-k dielectric layer and the metal layer; and

removing a portion of the metal layer to expose an upper portion of sidewalls of the trench.

2. The fabricating method of the semiconductor device according to claim 1, wherein the work function metal layer covers the upper portion of the sidewalls of the trench.

3. The fabricating method of the semiconductor device according to claim 2, further comprising:

forming a barrier layer and a filling metal layer on the work function metal layer.

4. The fabricating method of the semiconductor device according to claim 1, wherein removing a portion of the metal layer comprises the steps of:

filling a filling material in the trench;

etching back the filling material;

removing the portion of the metal layer; and

removing the filling material.

5. The fabricating method of the semiconductor device according to claim 4, wherein the filling material comprises a photoresist material, a bottom anti-reflection coating (BARC) or a light absorbing Si-content polymer (DUO).