Short channel effect suppression

• US 10,141,310 B2
• Filed: 12/23/2014
• Issued: 11/27/2018
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Cheng-Yi, Yang, Yu-Lin, Ho, Chia-Cheng, Chiang, Hung-Li, Lai, Wei-Jen, Chen, Tzu-Chiang, Lee, Tsung-Lin, Yeh, Chih Chieh, Chang, Chih-Sheng, Yeo, Yee-Chia
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): Chi, Suberr
• Application Number:
  US14/581,905
• Publication Number:
  US 20160181244A1
• Time in Patent Office: 1,435 Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features, after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features, forming a semiconductor layer over the anti-punch-through features, and forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features;

performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features;

after the etching process, epitaxially forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features;

forming a semiconductor layer over the anti-punch-through features;

removing a portion of the isolation features to expose at least a portion of the anti-punch-through features; and

forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features.

2. The method of claim 1, wherein the anti-punch-through features comprise a higher doping concentration than the semiconductor layer.

3. The method of claim 1, wherein forming the semiconductor layer comprises performing an epitaxial growth process to for the semiconductor layer.

4. The method of claim 1, wherein the semiconductor layer comprises silicon germanium at a ratio of silicon to germanium within a range of about 1:

0.1-0.9.

5. The method of claim 1, wherein the semiconductor layer is doped with a p-type dopant.

6. The method of claim 1, further comprising:

forming a second set of semiconductor features, the second set of features being separated by isolation features; and

forming anti-punch-through features below a top surface of the features of the second set of semiconductor features, each of the anti-punch-through features of the second set of semiconductor features being at substantially equal depths.

7. The method of claim 6, wherein forming the anti-punch-through features of the second set of semiconductor features comprises one of:

performing an implanting process, performing a diffusion process, and performing an epitaxial growth process.

8. The method of claim 1, further comprising, performing an annealing process after forming the anti-punch-through features.

9. The method of claim 1, wherein the anti-punch-through features comprise a p-type dopant.

10. The method of claim 1, wherein the anti-punch-through features comprise a doping concentration within a range of 1×

10¹⁷/cm³-1×

10¹⁸/cm³ and the semiconductor layer comprises a doping concentration within a range of 1×

10¹⁵/cm³-1×

10¹⁶/cm³.

11. A method comprising:

for an n-type region, forming a first set of fin structures, the fin structures of the first set varying in size;

forming n-type anti-punch-through features in the fin structures of the first set, the n-type anti-punch-through feature being at substantially a same depth for each of the fin structures of the first set;

for a p-type region, forming a second set of fin structures, the fin structures of the second set varying in size; and

after forming the second set of fin structures, epitaxially forming p-type anti-punch-through features in the fin structures of the second set, the p-type anti-punch-through features being at different depths for each of the fin structures of the second set;

forming isolation features between the second set of fin structures, a top surface of the isolation features being below at least a portion of the p-type anti-punch-through features.

12. The method of claim 11, wherein forming the n-type anti-punch-through features comprises performing an ion implantation process to introduce dopants below a surface of the first set of fin structure.

13. The method of claim 11, wherein forming the p-type anti-punch-through features comprises performing an ion implantation process at a surface of the second set of fin structures.

14. The method of claim 11, further comprising, forming a silicon germanium layer on top of the p-type anti-punch-through features.

15. The method of claim 11, wherein different depths of the p-type anti-punch-through features are based on a size of corresponding fin structures.

16. The method of claim 15, wherein larger fin structures have deeper anti-punch-through features.

17. The method of claim 11, further comprising:

forming n-type transistors on the first set of fin structures; and

forming p-type transistors on the second set of fin structures.

18. A semiconductor device comprising:

a p-type region comprising;

a first set of fin structures, the fin structures of the first set varying in size, the fin structures of the first set each comprising;

a bottommost portion;

a channel portion disposed above the bottommost portion and having an n-type dopant at a first concentration; and

an epitaxially grown anti-punch-through feature extending from the bottommost portion to the channel portion and having an n-type dopant throughout at a second concentration greater than the first concentration, wherein the anti-punch-through feature of a first fin structure of the first set extends to a different depth than the anti-punch-through feature of a second fin structure of the first set;

a plurality of p-type transistors formed on the fin structures of the first set, the p-type transistors having varying dimensions; and

a number of isolation features positioned such that a top surface of the isolation features is below a first portion of each of the anti-punch-through features and above a second portion of each of the anti-punch-through features.

19. The semiconductor device of claim 18, further comprising:

an n-type region comprising;

a second set of fin structures, the fin structures of the second set varying in size, the fin structures of the second set comprising anti-punch-through features at substantially similar depths; and

a plurality of n-type transistors formed on the fin structures of the second set, the n-type transistors having varying channel lengths.

20. The semiconductor device of claim 19, wherein a channel material for the n-type transistors comprises silicon and a channel material for the p-type devices comprises silicon germanium.