Techniques for achieving multiple transistor fin dimensions on a single die

• US 10,141,311 B2
• Filed: 03/24/2014
• Issued: 11/27/2018
• Est. Priority Date: 03/24/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Glass, Glenn A., Murthy, Anand S.
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): Le, Long H
• Application Number:
  US15/115,852
• Publication Number:
  US 20170133377A1
• Time in Patent Office: 1,709 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

Claims

1. An integrated circuit including at least one transistor device, the integrated circuit comprising:

a first fin above and native to a substrate, the first fin having a channel region, wherein the first fin includes a first width (W1) in a sub-channel region below the channel region and a second width (W2) in the channel region, W1 is greater than 15 nanometers (nm), W2 is 15 nm or less, and W1 is at least 1 nm greater than W2; and

a second fin above and native to the substrate, the second fin having a channel region, wherein the second fin includes a third width (W3) in the channel region, and W3 is different from W2.

2. The integrated circuit of claim 1, wherein the channel region of the first fin includes a first height and the channel region of the second fin includes a second height, and wherein the first and second heights are different but by no more than 5 nanometers.

3. The integrated circuit of claim 1, wherein W1 is between 2 nanometers (nm) and 6 nm greater than W2.

4. The integrated circuit of claim 1, wherein W3 is within 1 nanometer of W1.

5. The integrated circuit of claim 1, further comprising a gate structure above the channel region of the first fin, the gate structure also adjacent two sides of the channel region of the first fin, such that the channel region of the first fin is between two portions of the gate structure.

6. The integrated circuit of claim 5, wherein at least a portion of the gate structure is also on a top surface of the sub-channel region of the first fin.

7. The integrated circuit of claim 1, further comprising:

a first source region and a first drain region, the first source and drain regions adjacent the channel region of the first fin; and

a second source region and a second drain region, the second source and drain regions adjacent the channel region of the second fin.

8. The integrated circuit of claim 1, wherein the at least one transistor device includes

a p-type metal oxide semiconductor (p-MOS) transistor device including the channel region of the first fin and

an n-type metal oxide semiconductor (n-MOS) transistor device including the channel region of the second fin.

9. The integrated circuit of claim 8, further comprising a complementary metal oxide semiconductor (CMOS) circuit including the p-MOS and n-MOS transistor devices.

10. An integrated circuit, comprising:

a first semiconductor fin having a channel portion and a sub-channel portion;

a first trench adjacent the first semiconductor fin;

a first isolation material in the first trench and in contact with the sub-channel portion of the first semiconductor fin;

a first gate structure at least partially in the first trench and in contact with the channel portion of the first semiconductor fin;

a second semiconductor fin having a channel portion and a sub-channel portion;

a second trench adjacent the second semiconductor fin;

a second isolation material in the second trench and in contact with the sub-channel portion of the second semiconductor fin; and

a second gate structure at least partially in the second trench and in contact with the channel portion of the second semiconductor fin;

wherein the channel portion of the first semiconductor fin has a first width, as measured in a cross-section passing through the sub-channel and channel portions of the first semiconductor fin and taken perpendicular to the first semiconductor fin, that is 2 to 6 nm greater than a corresponding first width of the second semiconductor fin, the first widths measured about midway the corresponding channel portion, and the first width of the second semiconductor fin is 10 nm or less but at least 5 nm; and

wherein the sub-channel portion of the first semiconductor fin further has a second width, as measured in the cross-section, that is within 1 nm of a corresponding second width of the second semiconductor fin, the second widths measured about midway the corresponding sub-channel portion, the second widths both being greater than 10 nm but less than 20 nm.

11. The integrated circuit of claim 10, further comprising first source/drain regions and second source/drain regions, the first channel portion between the first source and the first drain region, and the second channel portion between the second source and the second drain region, wherein at least one of the first source/drain regions and the second source/drain regions comprise a semiconductor material that is distinct from a semiconductor material of an underlying substrate.

12. The integrated circuit of claim 11, wherein the substrate is silicon and the first and second semiconductor fins extend from and are part of the substrate, and at the first source/drain regions and the second source/drain regions comprise silicon and germanium.

13. The integrated circuit of claim 10, further comprising a substrate, wherein substrate is silicon and the first and second semiconductor fins extend from and are part of the substrate.

14. The integrated circuit of claim 10, wherein the first semiconductor fin has a first height as measured from a bottom of the first trench to a top of the first semiconductor fin, and the second semiconductor fin has a second height as measured from a bottom of the second trench to a top of the second semiconductor fin, the second height being different than the first.

15. The integrated circuit of claim 14, wherein the first height of the first semiconductor fin is within 5 nm of the second height of the second semiconductor fin.

16. The integrated circuit of claim 10, wherein height of the channel portion of at least one of the first semiconductor fin and the second semiconductor fin is 20 nm or more.

17. The integrated circuit of claim 10, wherein height of the channel portion of at least one of the first semiconductor fin and the second semiconductor fin is 45 nm or more.

18. The integrated circuit of claim 10, wherein the first width of the channel portion of second semiconductor fin is a trimmed width that is 2 nm to 6 nm thinner than its pre-trimmed width.

19. The integrated circuit of claim 10, wherein the first widths of the channel portions of the first and second semiconductor fins are the same.

20. The integrated circuit of claim 10, wherein at least one of the first and second semiconductor fins has a rounded top.

21. The integrated circuit of claim 10, wherein the first semiconductor fin is taller than the second semiconductor fin.

22. The integrated circuit of claim 10, wherein the first and second gate structures each includes:

a gate dielectric structure on the channel portion of the corresponding semiconductor fin; and

a gate electrode structure on the gate dielectric structure.

23. The integrated circuit of claim 10, wherein the first and second semiconductor fins are tapered as a result of the fin forming process, and the tapered shape is shown in the cross-section at least in the sub-channel portion of the corresponding fin.

24. The integrated circuit of claim 10, wherein the second widths are both greater than 15 nm but less than 20 nm.