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Semiconductor memory device having an electrically floating body transistor

  • US 10,141,315 B2
  • Filed: 06/09/2017
  • Issued: 11/27/2018
  • Est. Priority Date: 10/04/2010
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • an array of memory cells formed in a semiconductor, the array comprising;

    a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells comprising;

    a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;

    a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, and the buried region is discontinuous along one direction;

    wherein said floating body region stores a charge level indicative of a state of the memory cell selected from at least first and second states;

    wherein said buried region is configured to generate impact ionization when the memory cell is in one of said first and second states, and wherein said buried region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and

    first control circuitry configured to provide electrical signals to said buried region.

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