Display device

• US 10,141,387 B2
• Filed: 02/24/2017
• Issued: 11/27/2018
• Est. Priority Date: 04/08/2016
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: InnoLux Corporation
• Inventors: Lius, Chandra, Lee, Kuanfeng, Hsu, Nai-Fang
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US15/441,329
• Publication Number:
  US 20170294497A1
• Time in Patent Office: 641 Days
• Field of Search: None
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78672 Polycrystalline or microcrystalline silicon transistor
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

A display device is disclosed, which includes: a substrate; a light emitting diode disposed above the substrate; a first transistor disposed above the substrate; and a second transistor disposed above the substrate. The first transistor includes: a first semiconductor layer; a first top gate electrode disposed above the first semiconductor layer; a first bottom gate electrode disposed under the first semiconductor layer; a first source electrode electrically connected to the first semiconductor layer; and a first drain electrode electrically connected to the first semiconductor layer, wherein the first drain electrode is electrically connected to the light emitting diode. In addition, the second transistor includes: a second semiconductor layer. Herein, one of the first semiconductor layer and the second semiconductor layer includes a first silicon semiconductor layer, and the other includes a first oxide semiconductor layer.

Claims

1. A display device, comprising:

a substrate;

a light emitting diode disposed above the substrate;

a first transistor disposed above the substrate and comprising;

a first semiconductor layer;

a first top gate electrode disposed above the first semiconductor layer;

a first bottom gate electrode disposed under the first semiconductor layer;

a first source electrode electrically connected to the first semiconductor layer; and

a first drain electrode electrically connected to the first semiconductor layer, wherein the first drain electrode is electrically connected to the light emitting diode; and

a second transistor disposed above the substrate and comprising a second semiconductor layer;

wherein one of the first semiconductor layer and the second semiconductor layer comprises a first silicon semiconductor layer, and the other comprises a first oxide semiconductor layer, wherein the second transistor further comprises a first gate electrode and a second gate electrode, the first gate electrode is disposed above the second semiconductor layer, and the second gate electrode is disposed under the second semiconductor layer, wherein the second transistor further comprises a second drain electrode electrically connected to the second semiconductor layer, and the second drain electrode is electrically connected to the first source electrode through a conductive line or by direct contact, wherein the second transistor further comprises a second source electrode electrically connected to the second semiconductor layer, and the second source electrode is electrically connected to the first drain electrode through a conductive line or by direct.

2. The display device of claim 1, wherein the first semiconductor layer comprises the first silicon semiconductor layer and the second semiconductor layer comprises the first oxide semiconductor layer.

3. The display device of claim 1, wherein the first semiconductor layer comprises the first oxide semiconductor layer and the second semiconductor layer comprises the first silicon semiconductor layer.

4. The display device of claim 1, wherein the first source electrode and the first drain electrode are disposed below the first top gate electrode.

5. The display device of claim 1, wherein the second semiconductor layer comprises two second semiconductor regions, and the two second semiconductor regions respectively overlap the first gate electrode and the second gate electrode.

6. The display device of claim 1, wherein the second transistor further comprises a seventh gate electrode, and the seventh gate electrode is disposed under the second semiconductor layer.

7. The display device of claim 1, wherein the second semiconductor layer comprises the first silicon semiconductor layer.

8. The display device of claim 1, wherein the first source electrode, the first drain electrode and the first semiconductor layer are integrated.

9. The display device of claim 1, further comprising a third transistor which is disposed above the substrate, wherein the third transistor comprises a third semiconductor layer, a third gate electrode and a fourth gate electrode, and the third gate electrode and the fourth gate electrode are disposed above the third semiconductor layer.

10. The display device of claim 9, wherein the third semiconductor layer comprises a second silicon semiconductor layer or a second oxide semiconductor layer.

11. The display device of claim 1, further comprising a fourth transistor which is disposed above the substrate, wherein the fourth transistor comprises a fourth semiconductor layer, a fifth gate electrode and a sixth gate electrode, the fifth gate electrode is disposed above the fourth semiconductor layer, and the sixth gate electrode is disposed under the fourth semiconductor layer.

12. The display device of claim 11, wherein the fourth semiconductor layer comprises a third oxide semiconductor layer or a third silicon semiconductor layer.

13. The display device of claim 1, further comprising a first capacitor, wherein the first capacitor comprises a capacitor electrode, and the capacitor electrode and the first drain electrode partially overlap.

14. The display device of claim 1, further comprising a second capacitor, wherein the second capacitor comprises a fifth semiconductor layer, and the fifth semiconductor layer and the first top gate electrode partially overlap.