Vertical power MOSFET and methods of forming the same

• US 10,141,421 B2
• Filed: 06/05/2017
• Issued: 11/27/2018
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Liu, Ruey-Hsin, Su, Po-Chih
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): Smith, Stephen C
• Application Number:
  US15/613,597
• Publication Number:
  US 20170271480A1
• Time in Patent Office: 540 Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a region, and are electrically interconnected. The region between the first and the second gate electrodes overlaps the doped semiconductor region.

Claims

1. A device comprising:

a semiconductor layer of a first conductivity type;

a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite to the first conductivity type;

a doped semiconductor region of the first conductivity type between and contacting the first and the second body regions, wherein the doped semiconductor region has a bottom portion extending into the semiconductor layer to separate a top surface layer of the semiconductor layer into a first region and a second region;

a gate dielectric layer over the first and the second body regions and the doped semiconductor region; and

a first gate electrode and a second gate electrode over the gate dielectric layer, and overlapping the first and the second body regions, respectively, wherein the first and the second gate electrodes are physically separated from each, and are electrically interconnected, and wherein the doped semiconductor region is overlapped by a region between the first and the second gate electrodes.

2. The device of claim 1, wherein all impurities of the first conductivity type in the bottom portion of the doped semiconductor region in combination have a first impurity concentration, and all impurities of the first conductivity type in the first region in combination have a second impurity concentration lower than the first impurity concentration.

3. The device of claim 1, wherein the doped semiconductor region has a top portion between the first body region and the second body region, and all impurities of the first conductivity type in the top portion of the doped semiconductor region in combination have a first impurity concentration, and all impurities of the second conductivity type in the first body region have a second impurity concentration lower than the first impurity concentration.

4. The device of claim 1 further comprising a conductive field plate comprising:

a first portion and a second portion directly over the first and the second gate electrodes, respectively; and

a third portion connecting the first portion to the second portion of the conductive field plate, wherein the conductive field plate is electrically connected to the first gate electrode and the second gate electrode.

5. The device of claim 1 further comprising a dielectric layer comprising:

a first portion directly over the first gate electrode;

a second portion directly over the second gate electrode; and

a third portion extending into the region between the first and the second gate electrodes.

6. The device of claim 5, wherein the gate dielectric layer comprises a portion extending into the region between the first and the second gate electrodes, and a top surface of the gate dielectric layer in the region between the first and the second gate electrodes contacts a bottom surface of the third portion of the dielectric layer to form a distinguishable interface.

7. The device of claim 5 further comprising:

a heavily doped region of the first conductivity type extending into the first body region, wherein an edge of the dielectric layer is co-terminus with an edge of the heavily doped region.

8. The device of claim 1 further comprising a source region comprising:

a first portion and a second portion directly over the first gate electrode and the second gate electrode, respectively; and

a third portion extending into the region between the first and the second gate electrodes.

9. A device comprising:

a semiconductor layer of a first conductivity type;

a first and a second body region over the semiconductor layer and having a second conductivity type opposite to the first conductivity type;

a doped semiconductor region of the first conductivity type between the first and the second body regions, wherein bottoms of the doped semiconductor region and the first and the second body regions are in contact with top surfaces of the semiconductor layer;

a gate dielectric layer over the first and the second body regions and the doped semiconductor region;

a first and a second gate electrode over the gate dielectric layer, and overlapping the first and the second body regions, respectively, wherein the first and the second gate electrodes are physically separated from each other by a region, and are electrically interconnected;

a source region comprising first portions over the first and the second body regions, and a second portion in the region between the first and the second gate electrodes, with the second portion of the source region being at a same level as portions of the first and the second gate electrodes; and

a drain region underlying the semiconductor layer and comprising metal, wherein the source region and the drain region are on opposite sides of a region that comprises the first and the second body regions.

10. The device of claim 9 further comprising a conductive field plate having a portion disposed in the region between the first and the second gate electrodes, wherein the conductive field plate is spaced apart from the doped semiconductor region by the gate dielectric layer, wherein the conductive field plate is physically separated from the source region.

11. The device of claim 10 further comprising a dielectric layer separating the conductive field plate from the first and the second gate electrodes.

12. The device of claim 11, wherein the dielectric layer and the gate dielectric layer have edges co-terminus with each other, and the edges of the dielectric layer and the gate dielectric layer are in contact with a same edge of the source region.

13. The device of claim 9 further comprising a heavily doped semiconductor region of the first conductivity type, wherein the heavily doped semiconductor region and the doped semiconductor region are on opposite sides of, and contacting, the first body region.

14. The device of claim 13, wherein a sidewall of the heavily doped semiconductor region contacts the source region.

15. The device of claim 9, wherein the gate dielectric layer comprises:

a first portion overlapped by the first gate electrode;

a second portion overlapped by the second gate electrode; and

a third portion physically connecting the first portion to the second portion, wherein the second portion of the source region overlaps the third portion.

16. A device comprising:

a semiconductor layer of a first conductivity type;

a first and a second body region in a surface region of the semiconductor layer and having a second conductivity type opposite to the first conductivity type;

a doped semiconductor region of the first conductivity type between the first and the second body regions, wherein bottoms of the doped semiconductor region and the first and the second body regions are in contact with top surfaces of the semiconductor layer;

a gate dielectric layer over the first and the second body regions and the doped semiconductor region;

a first and a second gate electrode over the gate dielectric layer, and overlapping the first and the second body regions, respectively, wherein the first and the second gate electrodes are physically separated, and are electrically interconnected;

a metal line connecting the first gate electrode to the second gate electrode;

a conductive field plate physically separated from the first gate electrode and the second gate electrode, wherein the conductive field plate is electrically connected to the metal line, and the conductive field plate comprising;

a first portion and a second portion directly over the first and the second gate electrodes, respectively; and

a third portion connecting the first portion to the second portion of the conductive field plate.

17. The device of claim 16, wherein the doped semiconductor region has an impurity concentration higher than an impurity concentration of the semiconductor layer.

18. The device of claim 16 further comprising:

a source region formed of a metal, and the source region comprises a portion directly over a region between the first and the second gate electrodes, wherein the source region and the conductive field plate are configured to be able to have different voltages.

19. The device of claim 18, wherein the first and the second gate electrodes are electrically connected to the conductive field plate.

20. The device of claim 16, wherein the conductive field plate comprises a portion extending into a region between the first and the second gate electrodes.