Semiconductor device

• US 10,141,453 B2
• Filed: 12/15/2015
• Issued: 11/27/2018
• Est. Priority Date: 12/25/2014
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Imai, Hajime, Daitoh, Tohru, Ochi, Hisao, Fujita, Tetsuo, Kitagawa, Hideki, Kikuchi, Tetsuo, Suzuki, Masahiko, Kawashima, Shingo
• Primary Examiner(s): Yechuri, Sitaramarao S
• Application Number:
  US15/539,541
• Publication Number:
  US 20170352765A1
• Time in Patent Office: 1,078 Days
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device (100) includes: a substrate (10); and a thin film transistor (5) supported on the substrate, the thin film transistor including a gate electrode (12), an oxide semiconductor layer (18), a gate insulating layer (20) provided between the gate electrode and the oxide semiconductor layer, and a source electrode (14) and a drain electrode (16) electrically connected to the oxide semiconductor layer, wherein: the drain electrode is shaped so as to project toward the oxide semiconductor layer; a width W1 and a width W2 satisfy a relationship |W1−W2|≤1 μm, where the width W1 is a width of the oxide semiconductor layer in a channel width direction of the thin film transistor, and the width W2 is a width of the drain electrode in a direction perpendicular to a direction in which the drain electrode projects; and the width W1 and the width W2 are 3 μm or more and 6 μm or less.

Claims

1. A semiconductor device comprising:

a substrate; and

a thin film transistor supported on the substrate, the thin film transistor including a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,

a signal line connected to the source electrode and a scanning line connected to the gate electrode, the scanning line extending along a first direction and the signal line extending along a second direction crossing the first direction,

wherein;

the drain electrode, the source electrode and the oxide semiconductor layer are arranged in line along either the first direction or the second direction;

the source electrode is shaped so as to project along the second direction, and the drain electrode is arranged so as to oppose the source electrode with the oxide semiconductor layer interposed therebetween;

the drain electrode is shaped so as to project toward the oxide semiconductor layer;

a width W1 and a width W2 satisfy a relationship |W1−

W2|≤

1 μ

m, where the width W1 is a width of the oxide semiconductor layer in a channel width direction of the thin film transistor, and the width W2 is a width of the drain electrode in a direction perpendicular to a direction in which the drain electrode projects;

the width W1 and the width W2 are 3 μ

m or more and 6 μ

m or less;

the oxide semiconductor layer and the drain electrode are misaligned from each other in the first direction; and

a width W3 is 1 μ

m or more and is less than the width W1, where the width W3 is a width in the first direction of an overlapping portion between the oxide semiconductor layer and the drain electrode.

2. The semiconductor device according to claim 1, wherein the gate electrode is a portion of the scanning line, and the scanning line including the gate electrode extends straight along the first direction.

3. The semiconductor device according to claim 1, wherein a connecting portion between the sign and line and the source electrode and an extension of the drain electrode opposing the source electrode are located on opposite sides of the scanning line therebetween.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is provided so as to extend past opposite edges of the scanning line.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes In, Ga and Zn.

6. The semiconductor device according, to claim 1, wherein the oxide semiconductor layer includes a crystalline portion.

7. The semiconductor device according to claim 1, wherein the thin film transistor is a channel-etch type TFT.

8. A semiconductor device comprising:

a substrate; and

a thin film transistor supported on the substrate, the thin film transistor including a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,

a signal line connected to the source electrode and a scanning line connected to the gate electrode, the scanning line extending along a first direction and the signal line extending along a second direction crossing the first direction,

wherein;

the drain electrode, the source electrode and the oxide semiconductor layer are arranged in line along either the first direction or the second direction;

the source electrode is a portion of the signal line that is connected to the oxide semiconductor layer;

the drain electrode is shaped to extend along the second direction past an edge of the scanning line so as to project onto the scanning line toward the oxide semiconductor layer;

a width W1 and a width W2 satisfy a relationship |W1−

W2|≤

1 μ

m, where the width W1 is a width of the oxide semiconductor layer in a channel width direction of the thin film transistor, and the width W2 is a width of the drain electrode in a direction perpendicular to a direction in which the drain electrode projects;

the width W1 and the width W2 are 3 μ

m or more and 6 μ

m or less; and

a length in the second direction of an overlapping portion between the oxide semiconductor layer and the drain electrode is 1 μ

m or more and is less than or equal to the width W1.

9. The semiconductor device according, to claim 8, wherein the oxide semiconductor layer is provided over the scanning line and within the scanning line so as not to extend past an edge of the scanning line.